summaryrefslogtreecommitdiff
path: root/include
AgeCommit message (Collapse)AuthorFilesLines
2018-05-08Merge remote-tracking branch ↵Peter Maydell5-29/+21
'remotes/riscv/tags/riscv-qemu-2.13-pull-20180506' into staging RISC-V: QEMU 2.13 Privileged ISA emulation updates Several code cleanups, minor specification conformance changes, fixes to make ROM read-only and add device-tree size checks. * Honour privileged ISA v1.10 counter enable CSRs. * Implements WARL behavior for CSRs that don't support writes * Past behavior of raising traps was non-conformant with the RISC-V Privileged ISA Specification v1.10. * Allow S-mode access to sstatus.MXR when priv ISA >= v1.10 * Sets mtval/stval to zero on exceptions without addresses * Past behavior of leaving the last value was non-conformant with the RISC-V Privileged ISA Specition v1.10. mtval/stval must be set on all exceptions; to zero if not supported. * Make ROMs read-only and implement device-tree size checks * Uses memory_region_init_rom and rom_add_blob_fixed_as * Adds hexidecimal instruction bytes to disassembly output. * Fixes missing break statement for rv128 disassembly. * Several code cleanups * Replacing hard-coded constants with enums * Dead-code elimination This is an incremental pull that contains 20 reviewed changes out of 38 changes currently queued in the qemu-2.13-for-upstream branch. # gpg: Signature made Sun 06 May 2018 00:27:37 BST # gpg: using DSA key 6BF1D7B357EF3E4F # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>" # gpg: aka "Michael Clark <mjc@sifive.com>" # gpg: aka "Michael Clark <michael@metaparadigm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F * remotes/riscv/tags/riscv-qemu-2.13-pull-20180506: RISC-V: Mark ROM read-only after copying in code RISC-V: No traps on writes to misa,minstret,mcycle RISC-V: Make mtvec/stvec ignore vectored traps RISC-V: Add mcycle/minstret support for -icount auto RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 RISC-V: Clear mtval/stval on exceptions without info RISC-V: Hardwire satp to 0 for no-mmu case RISC-V: Update E and I extension order RISC-V: Remove erroneous comment from translate.c RISC-V: Remove EM_RISCV ELF_MACHINE indirection RISC-V: Make virt header comment title consistent RISC-V: Make some header guards more specific RISC-V: Fix missing break statement in disassembler RISC-V: Include instruction hex in disassembly RISC-V: Remove unused class definitions RISC-V: Remove identity_translate from load_elf RISC-V: Use ROM base address and size from memmap RISC-V: Make virt board description match spike RISC-V: Replace hardcoded constants with enum values Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-06RISC-V: Make virt header comment title consistentMichael Clark1-1/+1
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Make some header guards more specificMichael Clark2-4/+4
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove unused class definitionsMichael Clark4-22/+0
Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark1-2/+0
Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark4-0/+16
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-04hw/arm/virt-acpi-build: Add smmuv3 node in IORT tablePrem Mallappa1-0/+15
This patch builds the smmuv3 node in the ACPI IORT table. The RID space of the root complex, which spans 0x0-0x10000 maps to streamid space 0x0-0x10000 in smmuv3, which in turn maps to deviceid space 0x0-0x10000 in the ITS group. The guest must feature the IOMMU probe deferral series (https://lkml.org/lkml/2017/4/10/214) which fixes streamid multiple lookup. This bug is not related to the SMMU emulation. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shannon Zhao <zhaoshenglong@huawei.com> Message-id: 1524665762-31355-14-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/virt: Add SMMUv3 to the virt boardPrem Mallappa1-0/+10
Add code to instantiate an smmuv3 in virt machine. A new iommu integer member is introduced in VirtMachineState to store the type of the iommu in use. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-13-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: SkeletonPrem Mallappa1-0/+87
This patch implements a skeleton for the smmuv3 device. Datatypes and register definitions are introduced. The MMIO region, the interrupts and the queue are initialized. Only the MMIO read operation is implemented here. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmu-common: VMSAv8-64 page table walkEric Auger1-0/+14
This patch implements the page table walk for VMSAv8-64. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Message-id: 1524665762-31355-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmu-common: IOMMU memory region and address space setupEric Auger1-0/+8
We set up the infrastructure to enumerate all the PCI devices attached to the SMMU and create an associated IOMMU memory region and address space. Those info are stored in SMMUDevice objects. The devices are grouped according to the PCIBus they belong to. A hash table indexed by the PCIBus pointer is used. Also an array indexed by the bus number allows to find the list of SMMUDevices. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmu-common: smmu base device and datatypesEric Auger1-0/+123
The patch introduces the smmu base device and class for the ARM smmu. Devices for specific versions will be derived from this base device. We also introduce some important datatypes. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2018-05-04' into ↵Peter Maydell7-43/+53
staging QAPI patches for 2018-05-04 # gpg: Signature made Fri 04 May 2018 08:59:16 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2018-05-04: qapi: deprecate CpuInfoFast.arch qapi: discriminate CpuInfoFast on SysEmuTarget, not CpuInfoArch qapi: change the type of TargetInfo.arch from string to enum SysEmuTarget qapi: add SysEmuTarget to "common.json" qapi: fill in CpuInfoFast.arch in query-cpus-fast qobject: Modify qobject_ref() to return obj qobject: Replace qobject_incref/QINCREF qobject_decref/QDECREF qobject: use a QObjectBase_ struct qobject: Ensure base is at offset 0 qobject: Use qobject_to() instead of type cast Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180504' into stagingPeter Maydell2-2/+3
First s390x pull request for 2.13. - new machine type - extend SCLP event masks - support configuration of consoles via -serial - firmware improvements: non-sequential entries in boot menu, support for indirect loading via .INS files in s390-netboot - bugfixes and cleanups # gpg: Signature made Fri 04 May 2018 08:19:57 BST # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180504: pc-bios/s390: Update firmware images s390-ccw: force diag 308 subcode to unsigned long pc-bios/s390-ccw/net: Add support for .INS config files pc-bios/s390-ccw/net: Use diag308 to reset machine before jumping to the OS pc-bios/s390-ccw/net: Split up net_load() into init, load and release parts pc-bios/s390-ccw: fix non-sequential boot entries (enum) pc-bios/s390-ccw: fix non-sequential boot entries (eckd) pc-bios/s390-ccw: fix loadparm initialization and int conversion pc-bios/s390-ccw: rename MAX_TABLE_ENTRIES to MAX_BOOT_ENTRIES pc-bios/s390-ccw: size_t should be unsigned hw/s390x: Allow to configure the consoles with the "-serial" parameter s390x/kvm: cleanup calls to cpu_synchronize_state() vfio-ccw: introduce vfio_ccw_get_device() s390x/sclp: extend SCLP event masks to 64 bits s390x: introduce 2.13 compat machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180504' ↵Peter Maydell3-1/+14
into staging ppc patch queue 2018-05-04 Second patch of patches for qemu-2.13 (or whatever the version ends up being called). Highlights are: * Preliminary patches for POWER9 hash MMU support for powernv * A number of cleanups fo pseries startup and LPCR handling * Remove support for explicitly allocated RMAs (which require kernel support that's been gone for 3+ years) * Some mac_newworld cleanups * A few bugfixes # gpg: Signature made Fri 04 May 2018 06:07:43 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.13-20180504: spapr: don't advertise radix GTSE if max-compat-cpu < power9 spapr: don't migrate "spapr_option_vector_ov5_cas" to pre 2.8 machines target/ppc: always set PPC_MEM_TLBIE in pre 2.8 migration hack mac_newworld: move wiring of macio IRQs to macio_newworld_realize() mac_newworld: remove pics IRQ array and wire up macio to OpenPIC directly uninorth: create new uninorth device spapr: Clean up handling of LPCR power-saving exit bits spapr: Move PAPR mode cpu setup fully to spapr code target/ppc: Delay initialization of LPCR_UPRT for secondary cpus spapr: Clean up LPCR updates from hypercalls spapr: Make a helper to set up cpu entry point state spapr: Remove unhelpful helpers from rtas_start_cpu() spapr: Clean up rtas_start_cpu() & rtas_stop_self() target/ppc: Add ppc_store_lpcr() helper spapr: Remove support for explicitly allocated RMAs target/ppc: add basic support for PTCR on POWER9 target/ppc: return a nil HPT base address on sPAPR machines Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04qobject: Modify qobject_ref() to return objMarc-André Lureau2-3/+9
For convenience and clarity, make it possible to call qobject_ref() at the time when the reference is associated with a variable, or argument, by making qobject_ref() return the same pointer as given. Use that to simplify the callers. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20180419150145.24795-5-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Useless change to qobject_ref_impl() dropped, commit message improved slightly] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-05-04qobject: Replace qobject_incref/QINCREF qobject_decref/QDECREFMarc-André Lureau2-23/+19
Now that we can safely call QOBJECT() on QObject * as well as its subtypes, we can have macros qobject_ref() / qobject_unref() that work everywhere instead of having to use QINCREF() / QDECREF() for QObject and qobject_incref() / qobject_decref() for its subtypes. The replacement is mechanical, except I broke a long line, and added a cast in monitor_qmp_cleanup_req_queue_locked(). Unlike qobject_decref(), qobject_unref() doesn't accept void *. Note that the new macros evaluate their argument exactly once, thus no need to shout them. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20180419150145.24795-4-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Rebased, semantic conflict resolved, commit message improved] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-05-04qobject: use a QObjectBase_ structMarc-André Lureau7-17/+26
By moving the base fields to a QObjectBase_, QObject can be a type which also has a 'base' field. This allows writing a generic QOBJECT() macro that will work with any QObject type, including QObject itself. The container_of() macro ensures that the object to cast has a QObjectBase_ base field, giving some type safety guarantees. QObject must have no members but QObjectBase_ base, or else QOBJECT() breaks. QObjectBase_ is not a typedef and uses a trailing underscore to make it obvious it is not for normal use and to avoid potential abuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20180419150145.24795-3-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-05-04qobject: Ensure base is at offset 0Marc-André Lureau1-3/+2
All QObject types have the base QObject as their first field. This allows the simplification of qobject_to(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20180419150145.24795-2-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Commit message paragraph on type casts dropped, to avoid giving the impression type casting would be okay] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-05-04mac_newworld: move wiring of macio IRQs to macio_newworld_realize()Mark Cave-Ayland1-1/+0
Since the macio device has a link to the PIC device, we can now wire up the IRQs directly via qdev GPIOs rather than having to use an intermediate array. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-05-04uninorth: create new uninorth deviceMark Cave-Ayland1-0/+11
Commit 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" added a TODO which was to convert the uninorth registers hack to a proper device. Move these registers to a new uninorth device, removing the old hacks from mac_newworld.c. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-05-04spapr: Make a helper to set up cpu entry point stateDavid Gibson1-0/+3
Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify make a helper which sets up the common entry state for both boot and secondary cpu threads. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
2018-05-03linux-user: remove useless padding in flock64 structureLaurent Vivier1-1/+1
Since commit 8efb2ed5ec ("linux-user: Correct signedness of target_flock l_start and l_len fields"), flock64 structure uses abi_llong for l_start and l_len in place of "unsigned long long" this should force them to be aligned accordingly to the target rules. So we can remove the padding field and the QEMU_PACKED attribute. I have compared the result of the following program before and after the change: cat -> flock64_dump <<EOF p/d sizeof(struct target_flock64) p/d &((struct target_flock64 *)0)->l_type p/d &((struct target_flock64 *)0)->l_whence p/d &((struct target_flock64 *)0)->l_start p/d &((struct target_flock64 *)0)->l_len p/d &((struct target_flock64 *)0)->l_pid quit EOF for file in build/all/*-linux-user/qemu-* ; do echo $file gdb -batch -nx -x flock64_dump $file 2> /dev/null done The sizeof() changes because we remove the QEMU_PACKED. The new size is 32 (except for i386 and m68k) and this is the real size of "struct flock64" on the target architecture. The following architectures differ: aarch64_be, aarch64, alpha, armeb, arm, cris, hppa, nios2, or1k, riscv32, riscv64, s390x. For a subset of these architectures, I have checked with the following program the new structure is the correct one: #include <stdio.h> #define __USE_LARGEFILE64 #include <fcntl.h> int main(void) { printf("struct flock64 %d\n", sizeof(struct flock64)); printf("l_type %d\n", &((struct flock64 *)0)->l_type); printf("l_whence %d\n", &((struct flock64 *)0)->l_whence); printf("l_start %d\n", &((struct flock64 *)0)->l_start); printf("l_len %d\n", &((struct flock64 *)0)->l_len); printf("l_pid %d\n", &((struct flock64 *)0)->l_pid); } [I have checked aarch64, alpha, hppa, s390x] For ARM, the target_flock64 becomes the EABI definition, so we need to define the OABI one in place of the EABI one and use it when it is needed. I have also fixed the alignment value for sh4 (to align llong on 4 bytes) (see c2e3dee6e0 "linux-user: Define target alignment size") [We should check alignment properties for cris, nios2 and or1k] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180502215730.28162-1-laurent@vivier.eu>
2018-05-03linux-user: ARM-FDPIC: Identify ARM FDPIC binariesChristophe Lyon1-0/+1
Define an ARM-specific version of elf_is_fdpic: FDPIC ELF objects are identified with e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC. Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180430080404.7323-3-christophe.lyon@st.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-04-30hw/s390x: Allow to configure the consoles with the "-serial" parameterThomas Huth2-1/+2
The consoles ("sclpconsole" and "sclplmconsole") can only be configured with "-device" and "-chardev" so far. Other machines use the convenience option "-serial" to configure the default consoles, even for virtual consoles like spapr-vty on the pseries machine. So let's support this option on s390x, too. This way we can easily enable the serial console here again with "-nodefaults", for example: qemu-system-s390x -no-shutdown -nographic -nodefaults -serial mon:stdio ... which is way shorter than typing: qemu-system-s390x -no-shutdown -nographic -nodefaults \ -chardev stdio,id=c1,mux=on -device sclpconsole,chardev=c1 \ -mon chardev=c1 The -serial parameter can also be used if you only want to see the QEMU monitor on stdio without using -nodefaults, but not the console output. That's something that is pretty impossible with the current code today: qemu-system-s390x -no-shutdown -nographic -serial none While we're at it, this patch also maps the second -serial option to the "sclplmconsole", so that there is now an easy way to configure this second console on s390x, too, for example: qemu-system-s390x -no-shutdown -nographic -serial null -serial mon:stdio Additionally, the new code is also smaller than the old one and we have less s390x-specific code in vl.c :-) I've also checked that migration still works as expected by migrating a guest with console output back and forth between a qemu-system-s390x that has this patch and an instance without this patch. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1524754794-28005-1-git-send-email-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-04-30s390x/sclp: extend SCLP event masks to 64 bitsClaudio Imbrenda1-1/+1
Extend the SCLP event masks to 64 bits. Notice that using any of the new bits results in a state that cannot be migrated to an older version. Signed-off-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Message-Id: <1520507069-22179-1-git-send-email-imbrenda@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-04-27Merge remote-tracking branch 'remotes/kraxel/tags/ui-20180427-pull-request' ↵Peter Maydell2-0/+2
into staging vnc: fix use-after-free. sdl2: gles support. vfio-display: add reset support. # gpg: Signature made Fri 27 Apr 2018 10:54:17 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20180427-pull-request: ui: introduce vfio_display_reset console: introduce dpy_gfx_update_full sdl: Allow OpenGL ES context creation sdl: Move DisplayOptions global to sdl2_console qapi: Parameter gl of DisplayType now accept an enum vnc: fix use-after-free Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-04-27console: introduce dpy_gfx_update_fullTina Zhang1-0/+1
dpy_gfx_update_full is used to do the whole display surface update. This function is proposed by Gerd Hoffmann. Signed-off-by: Tina Zhang <tina.zhang@intel.com> Message-id: 1524820266-27079-2-git-send-email-tina.zhang@intel.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-04-27spapr: Support ibm,dynamic-memory-v2 propertyBharata B Rao1-0/+1
The new property ibm,dynamic-memory-v2 allows memory to be represented in a more compact manner in device tree. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()David Gibson1-1/+1
As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this change will make some things simpler later on. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2018-04-27Add host_memory_backend_pagesize() helperDavid Gibson1-0/+2
There are a couple places (one generic, one target specific) where we need to get the host page size associated with a particular memory backend. I have some upcoming code which will add another place which wants this. So, for convenience, add a helper function to calculate this. host_memory_backend_pagesize() returns the host pagesize for a given HostMemoryBackend object. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
2018-04-27spapr: Introduce pseries-2.13 machine typeDavid Gibson1-0/+2
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27uninorth: rename UNINState to UNINHostStateMark Cave-Ayland1-6/+6
The existing UNINState actually represents the PCI/AGP host bridge stage so rename it accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27uninorth: move PCI IO (ISA) memory region into the uninorth deviceMark Cave-Ayland1-0/+1
Do this for both the uninorth main and uninorth u3 AGP buses, using the main PCI bus for each machine (this ensures the IO addresses still match those used by OpenBIOS). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27uninorth: use object link to pass OpenPIC object to uninorthMark Cave-Ayland1-1/+4
Now that the OpenPIC is wired up via the board, we can now remove our temporary PIC qdev pointer property and replace it with an object link instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27uninorth: introduce temporary pic_irqs device propertyMark Cave-Ayland1-0/+1
This is in preparation for moving the PCI bus wiring inside the uninorth host bridge devices. In the future it will be possible to remove this once the PICs have been switched to use qdev GPIOs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize()Mark Cave-Ayland1-1/+0
Since the macio device has a link to the PIC device, we can now wire up the IRQs directly via qdev GPIOs rather than having to use an intermediate array. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27heathrow: remove obsolete heathow_init() functionMark Cave-Ayland1-1/+1
Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27uninorth: move uninorth definitions into uninorth.hMark Cave-Ayland1-0/+51
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> [dwg: Added hw/hw.h #include as suggested by Philippe Mathieu-Daudé] Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-04-27sdl: Move DisplayOptions global to sdl2_consoleElie Tournier1-0/+1
Suggested-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Elie Tournier <elie.tournier@collabora.com> Message-id: 20180413135842.21325-3-tournier.elie@gmail.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-04-26xen: Remove now-obsolete xen_xc_domain_add_to_physmapIan Jackson1-22/+0
The last user was just removed; remove this function, accordingly. Signed-off-by: Ian Jackson <Ian.Jackson@eu.citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com>
2018-04-26xen: Use newly added dmops for mapping VGA memoryRoss Lagerwall1-0/+32
Xen unstable (to be in 4.11) has two new dmops, relocate_memory and pin_memory_cacheattr. Use these to set up the VGA memory, replacing the previous calls to libxc. This allows the VGA console to work properly when QEMU is running restricted (-xen-domid-restrict). Wrapper functions are provided to allow QEMU to work with older versions of Xen. Tweak the error handling while making this change: * Report pin_memory_cacheattr errors. * Report errors even when DEBUG_HVM is not set. This is useful for trying to understand why VGA is not working, since otherwise it just fails silently. * Fix the return values when an error occurs. The functions now consistently return -1 and set errno. CC: Ian Jackson <ian.jackson@eu.citrix.com> Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Reviewed-by: Ian Jackson <ian.jackson@eu.citrix.com> Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com>
2018-04-26xen: destroy_hvm_domain: Try xendevicemodel_shutdownIan Jackson1-0/+7
xc_interface_open etc. is not going to work if we have dropped privilege, but xendevicemodel_shutdown will if everything is new enough. xendevicemodel_shutdown is only availabe in Xen 4.10 and later, so provide a stub for earlier versions. Signed-off-by: Ian Jackson <Ian.Jackson@eu.citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
2018-04-26xen: move xc_interface compatibility fallback further up the fileIan Jackson1-7/+11
We are going to want to use the dummy xendevicemodel_handle type in new stub functions in the CONFIG_XEN_CTRL_INTERFACE_VERSION < 41000 section. So we need to provide that definition, or (as applicable) include the appropriate header, earlier in the file. (Ideally the newer compatibility layers would be at the bottom of the file, so that they can naturally benefit from the compatibility layers for earlier version. But that's rather too much for this series.) No functional change. Signed-off-by: Ian Jackson <Ian.Jackson@eu.citrix.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
2018-04-26xen: restrict: use xentoolcore_restrict_allIan Jackson1-35/+11
And insist that it works. Drop individual use of xendevicemodel_restrict and xenforeignmemory_restrict. These are not actually effective in this version of qemu, because qemu has a large number of fds open onto various Xen control devices. The restriction arrangements are still not right, because the restriction needs to be done very late - after qemu has opened all of its control fds. xentoolcore_restrict_all and xentoolcore.h are available in Xen 4.10 and later, only. Provide a compatibility stub. And drop the compatibility stubs for the old functions. Signed-off-by: Ian Jackson <Ian.Jackson@eu.citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
2018-04-26AccelClass: Introduce accel_setup_postIan Jackson1-0/+3
This is called just before os_setup_post. Currently none of the accelerators provide this hook, but the Xen one is going to provide one in a moment. Signed-off-by: Ian Jackson <Ian.Jackson@eu.citrix.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
2018-04-26vl.c: new function serial_max_hds()Peter Maydell1-2/+4
Create a new function serial_max_hds() which returns the number of serial ports defined by the user. This is needed only by spapr. This allows us to remove the MAX_SERIAL_PORTS define. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-14-peter.maydell@linaro.org
2018-04-26vl.c: Remove compile time limit on number of serial portsPeter Maydell1-2/+0
Instead of having a fixed sized global serial_hds[] array, use a local dynamically reallocated one, so we don't have a compile time limit on how many serial ports a system has. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-13-peter.maydell@linaro.org
2018-04-26superio: Don't use MAX_SERIAL_PORTS for serial port limitPeter Maydell1-1/+3
The superio device has a limit on the number of serial ports it supports which is really only there because it has a fixed-size array serial[]. This limit isn't related particularly to the global MAX_SERIAL_PORTS limit, so use a different #define for it. (In practice the users of superio only ever want 2 serial ports.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-12-peter.maydell@linaro.org
2018-04-26serial-isa: Use MAX_ISA_SERIAL_PORTS instead of MAX_SERIAL_PORTSPeter Maydell1-0/+3
The ISA serial port handling in serial-isa.c imposes a limit of 4 serial ports. This is because we only know of 4 IO port and IRQ settings for them, and is unrelated to the generic MAX_SERIAL_PORTS limit, though they happen to both be set at 4 currently. Use a new MAX_ISA_SERIAL_PORTS wherever that is the correct limit to be checking against. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180420145249.32435-11-peter.maydell@linaro.org
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-24 08:31:08 +0000