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2013-09-10target-arm: Prepare translation for AArch64 codeAlexander Graf1-25/+109
This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf1-2/+2
Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-6-git-send-email-peter.maydell@linaro.org [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Avoid "1 << 31" undefined behaviourPeter Maydell1-16/+16
Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. For consistency, we make all the CPSR_* constants unsigned, though the only one which triggers undefined behaviour is CPSR_N. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org
2013-08-20target-arm: Implement the generic timerPeter Maydell1-0/+18
The ARMv7 architecture specifies a 'generic timer' which is implemented via cp15 registers. Newer kernels will prefer to use this rather than a devboard-level timer. Implement the generic timer for TCG; for KVM we will already use the hardware's virtualized timer for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1376065080-26661-4-git-send-email-peter.maydell@linaro.org
2013-08-20target-arm: Support coprocessor registers which do I/OPeter Maydell1-1/+5
Add an ARM_CP_IO flag which an ARMCPRegInfo definition can use to indicate that the register's implementation does I/O and thus its accesses need to be surrounded by gen_io_start()/gen_io_end() in order for icount to work. Most notably, cp registers which implement clocks or timers need this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1376065080-26661-3-git-send-email-peter.maydell@linaro.org
2013-08-20target-arm: Make IRQ and FIQ gpio lines on the CPU objectPeter Maydell1-0/+3
Now that ARMCPU is a subclass of DeviceState, we can make the CPU's inbound IRQ and FIQ lines be simply gpio lines, which means we can remove the odd arm_pic shim. We retain the arm_pic_init_cpu() function as a backwards compatibility shim layer so we can convert the board models to get the IRQ and FIQ lines directly from the ARMCPU object one at a time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1375977856-25046-2-git-send-email-peter.maydell@linaro.org
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-15target-arm: add feature flag for ARMv8Mans Rullgard1-0/+1
Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-14/+0
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-25target-arm: Convert TCG to using (index,value) list for cp migrationPeter Maydell1-0/+69
Convert the TCG ARM target to using an (index,value) list for migrating coprocessors. The primary benefit of the (index,value) list is for passing state between KVM and QEMU, but it works for TCG-to-TCG migration as well and is a useful self-contained first step. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfoPeter Maydell1-1/+17
For reading and writing register values from the kernel for KVM, we need to provide accessor functions which are guaranteed to succeed and don't impose access checks, mask out unwritable bits, etc. Define new fields raw_readfn and raw_writefn for this purpose; these only need to be provided if there is a readfn or writefn already and it is not suitable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Allow special cpregs to have flags setPeter Maydell1-1/+1
Relax the "is this a valid ARMCPRegInfo type value?" check to permit "special" cpregs to have flags other than ARM_CP_SPECIAL set. At the moment none of the other flags are relevant for special regs, but the migration related flag we're about to introduce can apply here too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: port ARM CPU save/load to use VMStateJuan Quintela1-2/+0
Port the ARM CPU save/load code to use VMState. Some state is saved in a slightly different order to simplify things -- for example arrays are saved one after the other rather than 'striped', and we always save all 32 VFP registers even if the CPU happens to only have 16. Use one subsection for each feature. This means that we don't need to bump the version field each time that a new feature gets introduced. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed conflicts, updated to use cpu_class_set_vmsd(), updated with new/removed fields since original patch, changed to use custom VMStateInfo for cpsr rather than presave/postload hooks, corrected subsection names so vmload doesn't fail] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-1/+0
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-3/+1
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-05ARM: KVM: Add support for KVM on ARM architectureChristoffer Dall1-0/+1
Add basic support for KVM on ARM architecture. Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu> [PMM: Minor tweaks and code cleanup, switch to ONE_REG] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-02-16target-arm: Update ARMCPU to QOM realizefnAndreas Färber1-0/+1
Turn arm_cpu_realize() into a QOM realize function, no longer called via cpu.h prototype. To maintain the semantics of cpu_init(), set realized = true explicitly in cpu_arm_init(). Move GDB coprocessor registration, CPU reset and vCPU initialization into the realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-3/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
2012-10-05target-arm: Drop unused DECODE_CPREG_CRN macroPeter Maydell1-2/+0
This macro snuck through code review despite being unused; drop it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl1-4/+6
Convert code load functions and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-10target-arm: Fix typos in commentsPeter Maydell1-1/+1
Fix a variety of typos in comments in target-arm files. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell1-2/+5
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the full width of the register. Add the state fields for the top half and the 64 bit access path. Actual use of the top half of the register will come with the addition of the long-descriptor translation table format support. For the PAR we also need to correct the masking applied for 32 bit writes (there are no bits reserved if LPAE is implemented) and clear the high half when doing a 32 bit result VA-to-PA lookup. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell1-3/+3
Extend feature flags to 64 bits, as we've just run out of space in the 32 bit integer we were using for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell1-0/+2
Implement the privileged-execute-never (PXN) translation table bit. It is implementation-defined whether this is implemented, so we give it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an LPAE feature flag and the implication logic, as a placeholder for actually implementing LPAE at a later date. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell1-1/+1
Make target_phys_addr_t 64 bits for ARM targets, and set TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM boards where physical addresses really are 32 bits (except perhaps a slight performance hit on 32 bit hosts for system emulation) but allows us to implement the Large Physical Address Extensions for Cortex-A15, which mean 40 bit physical addresses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell1-27/+0
All the uses of ARM_CPUID() to vary behaviour have now been removed, so we can delete the ARM_CPUID_* macros now. The one exception is the TI915T/925T, because of its odd behaviour where the MIDR value can be changed at runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell1-2/+1
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MPIDRPeter Maydell1-0/+1
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell1-2/+0
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell1-2/+0
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell1-0/+3
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=15 registersPeter Maydell1-0/+1
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell1-10/+0
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell1-0/+201
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-05-10target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULLPeter Maydell1-1/+9
The macro definition of cpu_init meant that if cpu_arm_init() returned NULL this wouldn't result in cpu_init() itself returning NULL. This had the effect that "-cpu foo" for some unknown CPU name 'foo' would cause ARM targets to segfault rather than generating a useful error message. Fix this by making cpu_init a simple inline function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-27target-arm: Change cpu_arm_init() return type to ARMCPUAndreas Färber1-3/+4
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to obtain an ARMCPU through arm_env_get_cpu() in machine init code. This requires to adjust the inclusion site of cpu-qom.h and in turn, forward-looking, to homogenize its include order. cpu_init() must still return a CPUARMState for backwards and cross-target compatibility, so adjust the cpu_init macro. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21target-arm: Move feature bit settings to CPU init fnsPeter Maydell1-3/+3
Move the setting of the feature bits from cpu_reset_model_id() to each CPU's instance init function. This requires us to move the features field in CPUARMState so that it is not cleared on reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: remind to keep arm features in sync with linux-user/elfload.cBenoit Canet1-0/+4
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-06Userspace ARM BE8 supportPaul Brook1-2/+30
Add support for ARM BE8 userspace binaries. i.e. big-endian data and little-endian code. In principle LE8 mode is also possible, but AFAIK has never actually been implemented/used. System emulation doesn't have any useable big-endian board models, but should in principle work once you fix that. Dynamic endianness switching requires messing with data accesses, preferably with TCG cooperation, and is orthogonal to BE8 support. Signed-off-by: Paul Brook <paul@codesourcery.com> [PMM: various changes, mostly as per my suggestions in code review: * rebase * use EF_ defines rather than hardcoded constants * make bswap_code a bool for future VMSTATE macro compatibility * update comment in cpu.h about TB flags bit field usage * factor out load-code-and-swap into arm_ld*_code functions and get_user_code* macros * fix stray trailing space at end of line * added braces in disas.c to satisfy checkpatch ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-03-30ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.Andrew Towers1-0/+1
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu does not support ARM1156 at this time.) MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores. Reference: ARM DDI 0211H, 0290G, 0301H, 0360E. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html Without this change, the linux kernel will not boot with VFP support enabled under ARM1176 system emulation, due to the unconditional use of MVFR1 at the end of vfp_init() in arch/arm/vfp/vfpmodule.c: VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5 Internal error: Oops - undefined instruction: 0 [#1] Signed-off-by: Andrew Towers <atowers@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-29target-arm: Minimalistic CPU QOM'ificationAndreas Färber1-0/+1
Introduce only one non-abstract type TYPE_ARM_CPU and do not touch cp15 registers to not interfere with Peter's ongoing remodelling. Embed CPUARMState as first (additional) field of ARMCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-29target-arm: Drop cpu_arm_close()Andreas Färber1-1/+0
It's unused, so no need to QOM'ify it later. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-arm: Don't overuse CPUStateAndreas Färber1-5/+5
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25Add Cortex-A15 CPU definitionPeter Maydell1-0/+1
Add a definition of a Cortex-A15 CPU. Note that for the moment we do not implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc) This CPU model is sufficient to boot a Linux kernel which has been compiled for an A15 without LPAE enabled. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25Add dummy implementation of generic timer cp15 registersPeter Maydell1-0/+1
Add a dummy implementation of the cp15 registers for the generic timer (found in the Cortex-A15), just sufficient for Linux to decide that it can't use it. This requires at least CNTP_CTL and CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13arm: Add dummy support for co-processor 15's secure config registerRob Herring1-1/+2
Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05arm: add dummy A9-specific cp15 registersMark Langsdorf1-1/+5
Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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