summaryrefslogtreecommitdiff
path: root/target-arm/helper.c
AgeCommit message (Collapse)AuthorFilesLines
2009-11-22ARM atomic ops rewritePaul Brook1-84/+0
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM Cortex-A9 cpu supportPaul Brook1-1/+35
Basic Cortex-A9 support. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM FP16 supportPaul Brook1-0/+16
Implement the ARM VFP half precision floating point extensions. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-10-27target-arm: allow modifying vfp fpexc en bit onlyJuha Riihimäki1-1/+1
All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: fix sdiv helperAurelien Jarno1-0/+2
(INT32_MIN / -1) triggers an overflow, and the result depends on the host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a test to output the correct value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23target-arm: use clz32() instead of a for loopAurelien Jarno1-4/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-2/+2
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-2/+2
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori1-0/+1
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix correct reset value for ARM CP15 c1 auxiliary control registeraurel321-1/+1
According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary control register is 2, not zero (page 3.12). Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6771 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07clean build: Fix arm build warningsaurel321-1/+1
Fix remaining arm warnings - except for the mess in the NetWinder FP emulator. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-4/+0
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26Log reset events (Jan Kiszka)aliguori1-0/+6
Original idea&code by Kevin Wolf, split-up in two patches and added more archs. This patch introduces a flag to log CPU resets. Useful for tracing unexpected resets (such as those triggered by x86 triple faults). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19Implement flush-to-zero mode (denormal results are replaced with zero).pbrook1-1/+2
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19Implement default-NaN mode.pbrook1-0/+2
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19Implement ARMv7 cp15 cache ID registers.pbrook1-7/+25
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19Implement (very) basic Thumb2-EE support. This doesn't actually implementpbrook1-0/+11
EE state, just the associated system coprocessor registers. It is sufficient to keep OS setup and context switching code happy. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6104 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19Fix VFP fixed point conversion routines.pbrook1-1/+1
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19Implement ARMv7 MMU access permissions.pbrook1-1/+11
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-22Fix ARMv6 translation table base address calculation.pbrook1-21/+20
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-22Optimize redundant cp15 coprocessor access control register writes.pbrook1-3/+5
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5512 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-11Add GDB XML register description support.pbrook1-0/+62
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19ARMv6: fix SIMD add/sub carry flags (Vincent Palatin).balrog1-4/+4
After a quick code review, it seems to be a bad cut-n-paste between 16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by pair instead of one at a time. Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT carry" instead of "carry" (probably once again due to a copy of the substraction code which sets flags to "NOT borrow") git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4900 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).balrog1-3/+3
helper.c - copy reference c0_c2 to runtime c0_c2 and not c0_c1 op_helper.c - remove old code (PARAM1, probably some left over from old dyngen) that broke do_[us]sat translate.c - gen_smul_dual should sign-extend from 16 bit to 32 bit and not from 8 to 32 - disas_arm_insn: * smlalxy: that was completely wrong; now the addition is performed as for smlald * pkhtb: optional ASR not taken into account (similar * to [us]sat) * pkhtb/pkhbt: tmp2 is dead * smlald, smlsld, smuad, smusd, smlad, smlsd: rd * and rn swapped git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4898 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-02ARMv7-M interrupt stack alignment fix.pbrook1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4823 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-01Fix incorrect argument types.pbrook1-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4291 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-20Remove an unused field and fix some non-code typos.balrog1-3/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-20Correct more ARM VFP 32/64 and signed/unsigned typos.balrog1-2/+2
Fixes unreadable fonts in Maemo guest. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-14Add basic OMAP2 chip support.balrog1-0/+7
Add the OMAP242x (arm1136 core) initialisation with basic on-chip peripherals and update OMAP1 peripherals which are re-used in OMAP2. Make palmte.c and sd.c errors go to stderr. Allow disabling SD chipselect. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-13Store the right TCG temp (typo).balrog1-1/+1
Stops ARMv6 target from segfaulting early. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11Remove osdep.c/qemu-img code duplicationaurel321-0/+1
(Kevin Wolf) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11Fix few spelling issues in commentsaurel321-4/+4
(Stefan Weil) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4187 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-01ARM N=Z=1 flag fix.pbrook1-8/+6
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 14/16.pbrook1-24/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 13/16.pbrook1-6/+8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 12/16.pbrook1-12/+12
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 11/16.pbrook1-1/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4148 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 10/16.pbrook1-0/+363
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 9/16.pbrook1-4/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 7/16.pbrook1-0/+245
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 6/16.pbrook1-0/+29
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4143 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 4/16.pbrook1-2/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 2/16.pbrook1-0/+8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4139 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31ARM TCG conversion 1/16.pbrook1-0/+26
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-09Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.ths1-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24Thumb semihosting fixes.pbrook1-1/+10
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3729 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-13Prevent cpsr_write/_read be put out of line in op.o (fixes a segfault on ↵balrog1-0/+42
some platforms). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3633 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11ARMv7 support.pbrook1-181/+923
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10added cpu_model parameter to cpu_init()bellard1-8/+11
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-31Invalidate TLBs when domains are changed (Matthew Warton).balrog1-2/+1
Legalise cp15 pid register writes (Matthew Warton). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3494 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-05 03:46:21 +0000