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2015-11-24target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8Peter Maydell1-1/+11
In an LPAE format descriptor in ARMv8 the address field extends up to bit 47, not just bit 39. Correct the masking so we don't give incorrect results if the output address size is greater than 40 bits, as it can be for AArch64. (Note that we don't yet support the new-in-v8 Address Size fault which should be generated if any translation table entry or TTBR contains an address with non-zero bits above the most significant bit of the maximum output address size.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1448029971-9875-1-git-send-email-peter.maydell@linaro.org
2015-11-03target-arm: Add and use symbolic names for register banksSoren Brinkmann1-15/+22
Add BANK_<cpumode> #defines to index banked registers. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias1-7/+31
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-15-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias1-5/+17
Add support for applying S2 translation to 32bit S1 page-table walks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-13-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias1-2/+48
Add support for applying S2 translation to 64bit S1 page-table walks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-12-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias1-12/+20
Introduce ARMMMUFaultInfo to propagate MMU Fault information across the MMU translation code path. This is in preparation for adding Stage-2 translation. No functional changes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias1-8/+8
Avoid inline for get_phys_addr() to prepare for future recursive use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias1-4/+37
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-9-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias1-13/+101
The starting level for S2 pagetable walks is computed differently from the S1 starting level. Implement the S2 variant. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-8-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias1-15/+15
Rename granule_sz to stride to better match the reference manuals. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias1-11/+11
Remove the tsz variable and introduce inputsize. This simplifies the code a little and makes it easier to compare with the reference manuals. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias1-1/+17
Add support for AArch32 S2 negative t0sz. In preparation for using 40bit IPAs on AArch32. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias1-2/+3
Move declaration of t0sz and t1sz to the top of the function avoiding a mix of code and variable declarations. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias1-2/+2
Make t0sz and t1sz signed integers to match tsz and to make it easier to implement support for AArch32 negative t0sz. t1sz is changed for consistensy. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add HPFAR_EL2Edgar E. Iglesias1-0/+12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann1-0/+16
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Add MDCR_EL2Sergey Fedorov1-0/+12
Add the MDCR_EL2 register. We don't implement any of the debug-related traps this register controls yet, so currently it simply reads back as written. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message; moved non-dummy definition from debug_cp_reginfo to el2_cp_reginfo.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista1-2/+23
Added oslar_write function to OSLAR_EL1 sysreg, using a status variable in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked to the newly added read-only OSLSR_EL1 register. Linux reads from this register during its suspend/resume procedure. Signed-off-by: Davorin Mista <davorin.mista@aggios.com> [PMM: folded a long line and tweaked a comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin1-2/+13
It is incorrect to call arm_el_is_aa64() function for unimplemented EL. This patch fixes several attempts to do so. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: Reworked several of the comments to be more verbose.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin1-1/+5
If any store instruction writes the code inside the same TB after this store insn, the execution of the TB must be stopped to execute new code correctly. As described in ARMv8 manual D3.4.6 self-modifying code must do an IC invalidation to be valid, and an ISB after it. So it's enough to end the TB after ISB instruction on the code translation. Also this TB break is necessary to take any pending interrupts immediately after an ISB (as required by ARMv8 ARM D1.14.4). Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: tweaked commit message and comments slightly] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Add missing 'static' attributeStefan Weil1-1/+1
Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1443213733-9807-1-git-send-email-sw@weilnetz.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-25arm: clarify the use of muldiv64()Laurent Vivier1-6/+8
muldiv64() is used to convert microseconds into CPU ticks. But it is not clear and not commented. This patch uses macro to clearly identify what is used: time, CPU frequency and ticks. For an elapsed time and a given frequency, we compute how many ticks we have. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-15target-arm: Use new revbit functionsRichard Henderson1-11/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias1-2/+24
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias1-1/+6
Break out mpidr_read_val() to allow future sharing of the code that conditionally sets the M and U bits of MPIDR. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-8-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias1-1/+41
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-7-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias1-2/+4
Stage-2 translations, EL2 and EL3 regimes don't have the EPD control. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-6-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias1-1/+3
Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias1-2/+32
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias1-2/+41
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed typo in comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-2/+2
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange1-1/+1
Many source files have doubled words (eg "the the", "to to", and so on). Most of these can simply be removed, but a couple were actual mis-spellings (eg "to to" instead of "to do"). There was even one triple word score "to to to" :-) Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias1-0/+6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1441311266-8644-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias1-4/+4
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1441311266-8644-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin1-32/+32
There is an error in functions aarch64_sync_32_to_64() and aarch64_sync_64_to_32() with mapping of registers between AArch32 and AArch64. This commit fixes the mapping to match the v8 ARM ARM section D1.20.1 (table D1-77). Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1440796451-15276-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tidied commit message a bit] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite1-1/+1
All of these hw_errors are fatal and indicate something wrong with QEMU implementation. Convert to g_assert_not_reached. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 169194d09017e5725535d31a1507d454c0043706.1440842587.git.crosthwaite.peter@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington1-3/+9
Print semihosting debugging information before the do_arm_semihosting() call so that angel_SWIreason_ReportException, which causes the function to not return, gets the same debug prints as other semihosting calls. Also print out the semihosting call number. Signed-off-by: Christopher Covington <christopher.covington@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Christopher Covington <cov@codeaurora.org> Message-id: 1439483745-28752-3-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell1-0/+55
Implement the AArch64 TLBI operations which take an intermediate physical address and invalidate stage 2 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell1-0/+76
Implement the remaining stage 1 TLB invalidate operations visible from EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-6-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell1-0/+22
Implement the missing TLBI operations that exist only if EL2 is implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-5-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell1-43/+129
Now we have the ability to flush the TLB only for specific MMU indexes, update the AArch64 TLB maintenance instruction implementations to only flush the parts of the TLB they need to, rather than doing full flushes. We take the opportunity to remove some duplicate functions (the per-asid tlb ops work like the non-per-asid ones because we don't support flushing a TLB only by ASID) and to bring the function names in line with the architectural TLBI operation names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-4-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell1-8/+8
Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the whole set of AArch64 TLBI regdefs is arranged in numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-3-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell1-0/+22
Implement the AArch32 ATS1H* operations which perform Hyp mode stage 1 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-6-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell1-5/+11
Apply the correct conditions in the ats_access() function for the ATS12NSO* address translation operations: * succeed at EL2 or EL3 * normal UNDEF trap from NS EL1 * trap to EL3 from S EL1 (only possible if EL3 is AArch64) (This change means they're now available in our EL3-supporting CPUs when they would previously always UNDEF.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-5-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell1-2/+41
Wire up the AArch64 EL2 and EL3 address translation operations (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some errors in the ats_write64() function in previously unused code that would have done the wrong kind of lookup for accesses from EL3 when SCR.NS==0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-3-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell1-0/+5
For EL2 stage 1 translations, there is no TTBR1. We were already handling this for 64-bit EL2; add the code to take the 'no TTBR1' code path for 64-bit EL2 as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-2-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell1-6/+15
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and ACTLR_EL3, for consistency. Since we don't currently have any CPUs that need the EL2/EL3 versions to reset to non-zero values, implement as RAZ/WI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing AFSR registersPeter Maydell1-0/+24
The AFSR registers are implementation dependent auxiliary fault status registers. We already implemented a RAZ/WI AFSR0_EL1 and AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-4-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Implement missing AMAIR registersPeter Maydell1-0/+21
The AMAIR registers are for providing auxiliary implementation defined memory attributes. We already implemented a RAZ/WI AMAIR_EL1; add the EL2 and EL3 versions for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-3-git-send-email-peter.maydell@linaro.org
2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell1-0/+8
Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only two which we had implemented the 32-bit Secure equivalents of but not the 64-bit Secure versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-2-git-send-email-peter.maydell@linaro.org
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