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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2014-08-29target-arm: Implement pmccfiltr_write functionAlistair Francis1-0/+9
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis1-23/+4
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis1-0/+23
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis1-0/+12
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis1-6/+39
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite1-1/+10
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis1-10/+9
2014-08-19target-arm: Implement MDSCR_EL1 as having statePeter Maydell1-1/+3
2014-08-19target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell1-0/+4
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell1-7/+26
2014-08-19target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell1-14/+20
2014-08-19target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell1-3/+8
2014-08-19target-arm: Collect up the debug cp register definitionsPeter Maydell1-32/+53
2014-08-04target-arm: A64: fix TLB flush instructionsAlex Bennée1-2/+8
2014-08-04target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée1-2/+2
2014-08-04target-arm: Fix bit test in sp_el0_accessStefan Weil1-1/+1
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias1-0/+6
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias1-0/+8
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias1-6/+6
2014-06-24Fix new typos (found by codespell)Stefan Weil1-1/+1
2014-06-19target-arm: Add ULL suffix to calculation of page sizePeter Maydell1-1/+1
2014-06-19target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler1-18/+44
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell1-3/+3
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell1-19/+6
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell1-9/+8
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler1-14/+14
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-2/+1
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-1/+1
2014-05-27target-arm: A64: Register VBAR_EL3Edgar E. Iglesias1-0/+5
2014-05-27target-arm: A64: Register VBAR_EL2Edgar E. Iglesias1-0/+21
2014-05-27target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias1-1/+1
2014-05-27target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias1-0/+16
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias1-0/+4
2014-05-27target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias1-3/+3
2014-05-27target-arm: Make esr_el1 an arrayEdgar E. Iglesias1-5/+5
2014-05-27target-arm: Make elr_el1 an arrayEdgar E. Iglesias1-1/+2
2014-05-27target-arm: implement CPACR register logic for ARMv7Fabian Aggeler1-4/+28
2014-05-13target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell1-0/+7
2014-05-01target-arm: A64: Fix a typo when declaring TLBI opsEdgar E. Iglesias1-12/+12
2014-05-01target-arm: Make vbar_write 64bit friendly on 32bit hostsEdgar E. Iglesias1-1/+1
2014-05-01target-arm: Implement XScale cache lockdown operations as NOPsPeter Maydell1-0/+15
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-6/+33
2014-04-17target-arm: Implement RVBAR registerPeter Maydell1-0/+6
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell1-29/+24
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell1-0/+9
2014-04-17target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell1-5/+91
2014-04-17target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell1-18/+43
2014-04-17target-arm: Implement ISR_EL1 registerPeter Maydell1-0/+18
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