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2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell1-0/+8
Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only two which we had implemented the 32-bit Secure equivalents of but not the 64-bit Secure versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1438281398-18746-2-git-send-email-peter.maydell@linaro.org
2015-08-13target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell1-0/+27
If EL3 is AArch32, then the secure physical timer is accessed via banking of the registers used for the non-secure physical timer. Implement this banking. Note that the access controls for the AArch32 banked registers remain the same as the physical-timer checks; they are not the same as the controls on the AArch64 secure timer registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell1-0/+87
On CPUs with EL3, there are two physical timers, one for Secure and one for Non-secure. Implement this extra timer and the AArch64 registers which access it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell1-1/+1
It's easy to accidentally define two cpregs which both try to reset the same underlying state field (for instance a clash between an AArch64 EL3 definition and an AArch32 banked register definition). if the two definitions disagree about the reset value then the result is dependent on which one happened to be reached last in the hashtable enumeration. Add a consistency check to detect and assert in these cases: after reset, we run a second pass where we check that the reset operation doesn't change the value of the register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436797559-20835-1-git-send-email-peter.maydell@linaro.org
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias1-0/+68
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1436791864-4582-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-13target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias1-22/+77
Prepare for adding the Hypervisor timer, no functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1436791864-4582-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-13target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias1-7/+5
Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1436791864-4582-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias1-2/+31
Adds control for trapping selected timer and counter accesses to EL2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436791864-4582-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias1-6/+41
Adds support for the virtual timer offset controlled by EL2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436791864-4582-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-15target-arm: Fix broken SCTLR_EL3 resetPeter Maydell1-0/+1
The SCTLR_EL3 cpreg definition was implicitly resetting the register state to 0, which is both wrong and clashes with the reset done via the SCTLR definition (since sctlr[3] is unioned with sctlr_s). This went unnoticed until recently, when an unrelated change (commit a903c449b41f105aa) happened to perturb the order of enumeration through the cpregs hashtable for reset such that the erroneous reset happened after the correct one rather than before it. Fix this by marking SCTLR_EL3 as an alias, so its reset is left up to the AArch32 view. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov1-1/+1
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1435676538-31345-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae1-3/+4
Remove semihosting_enabled and semihosting_target and replace them with SemihostingConfig structure containing equivalent fields. The structure is defined in vl.c where it is actually set. Also introduce separate header file include/exec/semihost.h allowing to access semihosting config related stuff from target specific semihosting code. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434643256-16858-2-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite1-1/+173
Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: dcb03cda6dd754c5cc6a962fa11f25089811e954.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite1-7/+83
Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 172cf135fbd8f5cea413c00e71cc1c3cac704744.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite1-0/+10
Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 9f248950b803a08c8b3c978931663182f7e882e7.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov1-19/+9
cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1434554713-10220-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: helper: rename get_phys_addr_mpuPeter Crosthwaite1-5/+5
This get_phys_addr is really for pmsav5. Rename it accordingly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: bf4b019aa87d682a45998105ef8e4d4e97a5e117.1434066412.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Implement uniprocessor with MP configPeter Crosthwaite1-2/+4
Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Refactor get_phys_addr FSR return mechanismPeter Crosthwaite1-58/+70
Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a209e3d8ae00cda55260c970891f520210e26bad.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: helper: Factor out CP regs common to [pv]msaPeter Crosthwaite1-9/+14
V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 284db78a43c63c9bfbb60de539672c361bcb6af8.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Don't add v7mp registers in MPU systemsPeter Crosthwaite1-1/+2
These registers are VMSA specific so they should be conditional on VMSA (i.e. !MPU). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7bb8843e45f2635c6b7a583c5bb5da51ed4442a0.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Do not define TLBTR in PMSA systemsPeter Crosthwaite1-3/+10
If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b03fea3840207edf633f5c9189400c3dd6a28d14.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin1-6/+3
When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: add AArch32 MIDR aliases in ARMv8Sergey Fedorov1-3/+7
According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-3-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Fix REVIDR reset valueSergey Fedorov1-3/+2
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-2-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: use extended address bits from supersection short descriptorSergey Fedorov1-0/+2
Since ARMv7 with LPAE support, a supersection short translation table descriptor has had extended base address fields which hold bits 39:32 of translated address. These fields are IMPDEF in ARMv6 and ARMv7 without LPAE support. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433235718-30485-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Handle "extended small page" descriptors correctlyPeter Maydell1-4/+9
The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1432844085-16441-1-git-send-email-peter.maydell@linaro.org
2015-06-02target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arraysPeter Maydell1-4/+4
The ARMCPRegInfo arrays v8_el3_no_el2_cp_reginfo and v8_el2_cp_reginfo are actually used on non-v8 CPUs as well. Remove the incorrect v8_ prefix from their names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1433182716-6400-1-git-send-email-peter.maydell@linaro.org
2015-06-02Revert "target-arm: Avoid g_hash_table_get_keys()"Markus Armbruster1-10/+2
Since we now require GLib 2.22+ (commit f40685c), we don't have to work around lack of g_hash_table_get_keys() anymore. This reverts commit 82a3a11897308b606120f7235001e87809708f85. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-id: 1432749090-4698-1-git-send-email-armbru@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TLBI_VAE2{IS}Edgar E. Iglesias1-0/+8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-11-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TLBI_ALLE2Edgar E. Iglesias1-0/+4
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-10-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TLBI_ALLE1{IS}Edgar E. Iglesias1-0/+8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TTBR0_EL2Edgar E. Iglesias1-0/+14
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-8-git-send-email-edgar.iglesias@gmail.com [PMM: Switch to preferred opc1/crm order for 64-bit AArch32 cpregs; drop unneeded use of vmsa_ttbr_writefn] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TPIDR_EL2Edgar E. Iglesias1-0/+7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-7-git-send-email-edgar.iglesias@gmail.com [PMM: reordered fields into preferred opc0/opc1/crn/crm/opc2 order] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add SCTLR_EL2Edgar E. Iglesias1-0/+7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-6-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TCR_EL2Edgar E. Iglesias1-0/+8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add MAIR_EL2Edgar E. Iglesias1-0/+15
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Break down TLB_LOCKDOWNEdgar E. Iglesias1-12/+18
Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Add AArch64 CPTR registersGreg Bellows1-1/+39
Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows1-37/+4
Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell1-40/+7
Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-18target-arm: Remove unneeded '+'Edgar E. Iglesias1-1/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1431499963-1019-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Correct accessfn for CNTV_TVAL_EL0Edgar E. Iglesias1-0/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1431499963-1019-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Correct accessfn for CNTP_{CT}VAL_EL0Edgar E. Iglesias1-1/+2
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1431499963-1019-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Add EL3 and EL2 TCR checkingGreg Bellows1-13/+32
Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-8-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Add TTBR regime function and useGreg Bellows1-5/+19
Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-7-git-send-email-greg.bellows@linaro.org [PMM: fixed regime_ttbr() return type to be uint64_t] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-14tcg: Push merged memop+mmu_idx parameter to softmmu routinesRichard Henderson1-4/+6
The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-04-26Allow ARMv8 SCR.SMD updatesGreg Bellows1-1/+3
Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8 regardless of whether virtualization (EL2) is enabled or not. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1429888797-4378-1-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-26target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov1-2/+2
Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> [PMM: also fixed a couple of missed occurrences in cpu.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-26target-arm: Add user-mode transaction attributePeter Maydell1-0/+1
Add a transaction attribute indicating that a memory access is being done from user-mode (unprivileged). This corresponds to an equivalent signal in ARM AMBA buses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-09 09:45:10 +0000