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2016-03-16target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell1-0/+3
Starting with the ARMv7 Virtualization Extensions, the A32 and T32 instruction sets provide instructions "MSR (banked)" and "MRS (banked)" which can be used to access registers for a mode other than the current one: * R<m>_<mode> * ELR_hyp * SPSR_<mode> Implement the missing instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1456762734-23939-1-git-send-email-peter.maydell@linaro.org
2016-03-04target-arm: implement setendPaolo Bonzini1-0/+1
Since this is not a high-performance path, just use a helper to flip the E bit and force a lookup in the hash table since the flags have changed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell1-0/+1
The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell1-1/+1
System registers might have access requirements which need to be described via a CPAccessFn and which differ for reads and writes. For this to be possible we need to pass the access function a parameter to tell it whether the access being checked is a read or a write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-6-git-send-email-peter.maydell@linaro.org
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov1-0/+2
A QEMU breakpoint match is not definitely an architectural breakpoint match. If an exception is generated unconditionally during translation, it is hardly possible to ignore it in the debug exception handler. Generate a call to a helper to check CPU breakpoints and raise an exception only if any breakpoint matches architecturally. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell1-0/+1
Currently we use DISAS_WFE for both WFE and YIELD instructions. This is functionally correct because at the moment both of them are implemented as "yield this CPU back to the top level loop so another CPU has a chance to run". However it's rather confusing that YIELD ends up calling HELPER(wfe), and if we ever want to implement real behaviour for WFE and SEV it's likely to trip us up. Split out the yield codepath to use DISAS_YIELD and a new HELPER(yield) function, and have HELPER(wfe) call HELPER(yield). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1435672316-3311-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows1-1/+1
Add a CPU state exception target EL field that will be used for communicating the EL to which an exception should be routed. Add a disassembly context field for tracking the EL3 architecture needed for determining the target exception EL. Add a target EL argument to the generic exception helper for callers to specify the EL to which the exception should be routed. Extended the helper to set the newly added CPU state exception target el. Added a function for setting the target exception EL and updated calls to helpers to call it. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-0/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-8-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell1-0/+1
Implement ARMv8 software single-step handling for A64 code: correctly update the single-step state machine and generate debug exceptions when stepping A64 code. This patch has no behavioural change since MDSCR_EL1.SS can't be set by the guest yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell1-2/+0
The iwmmxt_msadb helper and its corresponding gen function are unused; delete them. (This function appears to have never been used right back to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq, and is presumably an accidental remnant from the initial development.) Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401822125-1822-1-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell1-0/+3
Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication instruction in the A32/T32 instruction sets; this is part of the v8 Crypto Extensions. To do this we have to move the neon_pmull_64_{lo,hi} helpers from helper-a64.c into neon_helper.c so they can be used by the AArch32 translator. Inspired-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-4-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel1-0/+9
This adds support for the SHA1 and SHA256 instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org [PMM: * rebase * fix bad indent * add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case * use g_assert_not_reached() * don't re-extract bit 6 for the 2-reg-misc encodings * set the ELF HWCAP2 bits for the new features ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-4/+0
Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+1
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or AArch32 EL0 are supported. Signed-off-by: Rob Herring <rob.herring@linaro.org> [PMM: fixed minor style nits; updated to match changes in previous patches; added some of the simpler cases of illegal-exception-return support] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-0/+1
Implement the DC ZVA instruction, which clears a block of memory. The fast path obtains a pointer to the underlying RAM via the TCG TLB data structure so we can do a direct memset(), with fallback to a simple byte-store loop in the slow path. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Add support for generating exceptions with syndrome informationPeter Maydell1-1/+2
Add new helpers exception_with_syndrome (for generating an exception with syndrome information) and exception_uncategorized (for generating an exception with "Unknown or Uncategorized Reason", which have a syndrome register value of zero), and use them to generate the correct syndrome information for exceptions which are raised directly from generated code. This patch includes moving the A32/T32 gen_exception_insn functions further up in the source file; they will be needed for "VFP/Neon disabled" exception generation later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell1-1/+1
For exceptions taken to AArch64, if a coprocessor/system register access fails due to a trap or enable bit then the syndrome information must include details of the failing instruction (crn/crm/opc1/opc2 fields, etc). Make the decoder construct the syndrome information at translate time so it can be passed at runtime to the access-check helper function and used as required. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-03-18target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée1-6/+14
Add the saturating accumulate operations USQADD and SUQADD to the A64 instruction set. This completes coverage of A64 Neon. These operations (which are unsigned + signed -> signed and signed + unsigned -> unsigned) don't exist in the A32/T32 instruction set, so require a complete new set of helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-18target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée1-6/+8
This mostly re-uses the existing NEON helpers with an additional two for the 64 bit case. I also took the opportunity to add TCG_CALL_NO_RWG options to the helpers as they don't modify globals (saturation flags are in the CPU Environment). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée1-2/+3
This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée1-2/+3
Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
2014-03-10target-arm: Implement WFE as a yield operationPeter Maydell1-0/+1
Implement WFE to yield our timeslice to the next CPU. This avoids slowdowns in multicore configurations caused by one core busy-waiting on a spinlock which can't possibly be unlocked until the other core has an opportunity to run. This speeds up my test case A15 dual-core boot by a factor of three (though it is still four or five times slower than a single-core boot). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393339545-22111-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Rob Herring <rob.herring@linaro.org>
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton1-0/+3
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8 and add a CPU feature flag to enable these instructions. The CRC32-C implementation used is the built-in qemu implementation and The CRC-32 implementation is from zlib. This requires adding zlib to LIBS to ensure it is linked for the linux-user binary. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393411566-24104-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell1-0/+2
Implement the MSR (immediate) instructions, which can update the PSTATE SP and DAIF fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell1-0/+1
Several of the system registers handled via the ARMCPRegInfo mechanism have access trap control bits controlling whether the registers are accessible to lower privilege levels. Replace the existing mechanism (allowing the read and write functions to return EXCP_UDEF if access is denied) with a dedicated "check access rights" function pointer in the ARMCPRegInfo. This will allow us to simplify some of the register definitions, which no longer need read/write functions purely to handle the access checks. We take the opportunity to define the return value from the access checking function in a way that allows us to set the correct exception syndrome information for exceptions taken to AArch64 (which may need to distinguish access failures due to a configurable trap or enable from other kinds of access failure). This commit defines the new mechanism but does not move any of the registers across to use it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell1-0/+2
Implement the remaining instructions in the SIMD 3-reg-same and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE, FACGT, FMLA and FMLS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell1-0/+1
Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: Add set_neon_rmode helperWill Newton1-0/+1
This helper sets the rounding mode in the standard_fp_status word to allow NEON instructions to modify the rounding mode whilst using the standard FPSCR values for everything else. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell1-0/+2
Add support for FCVT between half, single and double precision. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell1-0/+5
This patch adds support for those instructions in the "Floating-point data-processing (1 source)" group which are simple 32-bit-to-32-bit or 64-bit-to-64-bit operations (ie everything except FCVT between single/double/half precision). We put the new round-to-int helpers in helper.c because they will also be used by the new ARMv8 A32/T32 rounding instructions. Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, merged single and double precision patches, updated to new infrastructure.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: reworked decode, split FCVT out into their own patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf1-0/+2
This patch adds emulation for the instruction group labeled "Floating-point <-> fixed-point conversions" in the ARM ARM. Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU (scalar, fixed-point). Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, rebased, updated to new infrastructure. Applied bug fixes from Michael Matz and Janne Grunau.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: significant cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add extra VFP fixed point conversion helpersWill Newton1-0/+16
Define the full set of floating point to fixed point conversion helpers required to support AArch64. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Rename A32 VFP conversion helpersWill Newton1-8/+8
The VFP conversion helpers for A32 round to zero as this is the only rounding mode supported. Rename these helpers to make it clear that they round to zero and are not suitable for use in the AArch64 code. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell1-7/+8
Use the VFP_BINOP macro to provide helpers for min, max, minnum and maxnum, rather than hand-rolling them. (The float64 max version is not used by A32 but will be needed for A64.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf1-0/+4
We will need helpers that only make sense with AArch64. Add helper-a64.{c,h} files as stubs that we can fill with these helpers in the following patches. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel1-0/+3
This adds support for the AESE/AESD/AESMC/AESIMC instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton1-0/+5
This adds support for the ARMv8 floating point VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-4/+4
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23target-arm: Implement sbc_cc inlineRichard Henderson1-2/+0
Use sub2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Implement adc_cc inlineRichard Henderson1-1/+0
Use add2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson1-2/+0
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-28target-arm: rename helper flagsAurelien Jarno1-8/+8
Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Cc: Paul Brook <paul@codesourcery.com> Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-24target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell1-1/+0
Implement abs_i32 inline (with movcond) rather than using a helper function. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell1-1/+0
Use the TCG operation to do Neon 64 bit negations rather than calling a helper routine for it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: mark a few integer helpers const and pureAurelien Jarno1-9/+10
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno1-3/+0
Now that the movcond TCG op is available, it's possible to replace shl and shr helpers by TCG code. The code generated by TCG is slightly longer than the code generated by GCC for the helper but is still worth it as this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno1-2/+0
Now that the setcond TCG op is available, it's possible to replace add_cc and sub_cc helpers by TCG code. The code generated by TCG is actually very close to the one generated by GCC for the helper, and this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15target-arm: convert remaining helpersBlue Swirl1-26/+26
Convert remaining helpers to AREG0 free mode: add an explicit CPUState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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