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path: root/target-arm/helper.h
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2014-03-10target-arm: Implement WFE as a yield operationPeter Maydell1-0/+1
Implement WFE to yield our timeslice to the next CPU. This avoids slowdowns in multicore configurations caused by one core busy-waiting on a spinlock which can't possibly be unlocked until the other core has an opportunity to run. This speeds up my test case A15 dual-core boot by a factor of three (though it is still four or five times slower than a single-core boot). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393339545-22111-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Rob Herring <rob.herring@linaro.org>
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton1-0/+3
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8 and add a CPU feature flag to enable these instructions. The CRC32-C implementation used is the built-in qemu implementation and The CRC-32 implementation is from zlib. This requires adding zlib to LIBS to ensure it is linked for the linux-user binary. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393411566-24104-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell1-0/+2
Implement the MSR (immediate) instructions, which can update the PSTATE SP and DAIF fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell1-0/+1
Several of the system registers handled via the ARMCPRegInfo mechanism have access trap control bits controlling whether the registers are accessible to lower privilege levels. Replace the existing mechanism (allowing the read and write functions to return EXCP_UDEF if access is denied) with a dedicated "check access rights" function pointer in the ARMCPRegInfo. This will allow us to simplify some of the register definitions, which no longer need read/write functions purely to handle the access checks. We take the opportunity to define the return value from the access checking function in a way that allows us to set the correct exception syndrome information for exceptions taken to AArch64 (which may need to distinguish access failures due to a configurable trap or enable from other kinds of access failure). This commit defines the new mechanism but does not move any of the registers across to use it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell1-0/+2
Implement the remaining instructions in the SIMD 3-reg-same and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE, FACGT, FMLA and FMLS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell1-0/+1
Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: Add set_neon_rmode helperWill Newton1-0/+1
This helper sets the rounding mode in the standard_fp_status word to allow NEON instructions to modify the rounding mode whilst using the standard FPSCR values for everything else. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell1-0/+2
Add support for FCVT between half, single and double precision. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell1-0/+5
This patch adds support for those instructions in the "Floating-point data-processing (1 source)" group which are simple 32-bit-to-32-bit or 64-bit-to-64-bit operations (ie everything except FCVT between single/double/half precision). We put the new round-to-int helpers in helper.c because they will also be used by the new ARMv8 A32/T32 rounding instructions. Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, merged single and double precision patches, updated to new infrastructure.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: reworked decode, split FCVT out into their own patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf1-0/+2
This patch adds emulation for the instruction group labeled "Floating-point <-> fixed-point conversions" in the ARM ARM. Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU (scalar, fixed-point). Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, rebased, updated to new infrastructure. Applied bug fixes from Michael Matz and Janne Grunau.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: significant cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add extra VFP fixed point conversion helpersWill Newton1-0/+16
Define the full set of floating point to fixed point conversion helpers required to support AArch64. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Rename A32 VFP conversion helpersWill Newton1-8/+8
The VFP conversion helpers for A32 round to zero as this is the only rounding mode supported. Rename these helpers to make it clear that they round to zero and are not suitable for use in the AArch64 code. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell1-7/+8
Use the VFP_BINOP macro to provide helpers for min, max, minnum and maxnum, rather than hand-rolling them. (The float64 max version is not used by A32 but will be needed for A64.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf1-0/+4
We will need helpers that only make sense with AArch64. Add helper-a64.{c,h} files as stubs that we can fill with these helpers in the following patches. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel1-0/+3
This adds support for the AESE/AESD/AESMC/AESIMC instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton1-0/+5
This adds support for the ARMv8 floating point VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-4/+4
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23target-arm: Implement sbc_cc inlineRichard Henderson1-2/+0
Use sub2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Implement adc_cc inlineRichard Henderson1-1/+0
Use add2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson1-2/+0
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-28target-arm: rename helper flagsAurelien Jarno1-8/+8
Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Cc: Paul Brook <paul@codesourcery.com> Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-24target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell1-1/+0
Implement abs_i32 inline (with movcond) rather than using a helper function. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell1-1/+0
Use the TCG operation to do Neon 64 bit negations rather than calling a helper routine for it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: mark a few integer helpers const and pureAurelien Jarno1-9/+10
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno1-3/+0
Now that the movcond TCG op is available, it's possible to replace shl and shr helpers by TCG code. The code generated by TCG is slightly longer than the code generated by GCC for the helper but is still worth it as this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno1-2/+0
Now that the setcond TCG op is available, it's possible to replace add_cc and sub_cc helpers by TCG code. The code generated by TCG is actually very close to the one generated by GCC for the helper, and this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15target-arm: convert remaining helpersBlue Swirl1-26/+26
Convert remaining helpers to AREG0 free mode: add an explicit CPUState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15target-arm: convert void helpersBlue Swirl1-4/+4
Add an explicit CPUState parameter instead of relying on AREG0. For easier review, convert only op helpers which don't return any value. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell1-3/+0
There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TEECR, TEEHBR to new schemePeter Maydell1-2/+0
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell1-3/+0
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell1-0/+5
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell1-0/+3
Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22Revert "target-arm: Use global env in neon_helper.c helpers"Peter Maydell1-67/+67
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3 so that we return to passing CPUState to helpers as an explicit parameter. (There were a number of conflicts in target-arm/translate.c which had to be resolved by hand so it is not a pure revert.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Pass fp status pointer explicitly to neon fp helpersPeter Maydell1-11/+8
Make the Neon helpers for various floating point operations take an explicit pointer to the float_status they use, so they don't rely on the global environment pointer any more. This also allows us to drop the mul/sub/add helpers completely and just use the vfp versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUStatePeter Maydell1-8/+8
Make the VFP binop helper functions take a pointer to the fp status, not the entire CPUState. This will allow us to use them for Neon operations too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22Revert "target-arm: Use global env in iwmmxt_helper.c helpers"Peter Maydell1-61/+61
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79, returning the iwmmxt helpers to passing env in as a parameter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-05-23target-arm: Use correct float status for Neon int-float conversionsPeter Maydell1-30/+30
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helper functions take a pointer to the appropriate float_status value rather than simply taking a pointer to the entire CPUState, and making translate.c pass a pointer to vfp.fp_status or vfp.standard_fp_status appropriately for whether the instruction being translated is Neon or VFP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17move helpers.h to helper.hLluís1-0/+475
This provides a consistent naming scheme across all targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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