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2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell1-0/+6
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the full width of the register. Add the state fields for the top half and the 64 bit access path. Actual use of the top half of the register will come with the addition of the long-descriptor translation table format support. For the PAR we also need to correct the masking applied for 32 bit writes (there are no bits reserved if LPAE is implemented) and clear the high half when doing a 32 bit result VA-to-PA lookup. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell1-2/+2
Extend feature flags to 64 bits, as we've just run out of space in the 32 bit integer we were using for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell1-2/+0
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13arm: Add dummy support for co-processor 15's secure config registerRob Herring1-0/+2
Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05arm: add dummy A9-specific cp15 registersMark Langsdorf1-0/+6
Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm/machine.c: Restore VFP registers correctlyDmitry Koshelev1-1/+1
Fix the restoring of VFP registers on vmload. Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com> Reviewed-by: Juan Quintela <quintela@redhat.com> [peter.maydell: improved commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Minimal implementation of performance countersPeter Maydell1-0/+12
Newer Linux kernels assume the existence of the performance counter cp15 registers. Provide a minimal implementation of these registers. We support no events. This should be compliant with the ARM ARM, except that we don't implement the cycle counter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski1-0/+2
Implement VA->PA translations by cp15-c7 that went through unchanged previously. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-31Save/restore ARMv6 MMU statePaul Brook1-1/+21
Correctly save/restore ARMV6 MMU state. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-21Convert machine registration to use module init functionsAnthony Liguori1-25/+0
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-14Syborg (Symbian Virtual Platform) boardPaul Brook1-0/+1
A virtual reference platform for SymbianOS development/debugging. Signed-off-by: Paul Brook <paul@codesourcery.com>
2008-12-15ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).balrog1-0/+2
The TSC2102 chip is not included in documentation because a patch is pending. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13Remove unnecessary trailing newlinesblueswir11-2/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30Move CPU save/load registration to common code.pbrook1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-02Provide basic emulation for Sharp SL-6000 PDA (Tosa), Dmitry Baryshkov.balrog1-0/+1
This adds basic support for emulating Sharp Zaurus SL-6000 PDA (tosa). Currently it provides only basic support: no kbd/lcd, sound, ts, etc. But it's able at least to boot Linux from CF. Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4643 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-18Add N810 to allowed -M values, add documentation part for N8x0.balrog1-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4490 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04remove target ifdefs from vl.caurel321-0/+213
(Glauber Costa) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
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