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2014-11-02target-arm: A64: remove redundant storeAlex Bennée1-1/+0
There is not much point storing the same value twice in a row. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-8/+8
Renamed the arm_current_pl CPU function to more accurately represent that it returns the ARMv8 EL rather than ARMv7 PL. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-5-git-send-email-greg.bellows@linaro.org [PMM: fixed a minor merge resolution error in a couple of hunks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell1-2/+2
SMC must UNDEF if EL3 is not implemented; similarly HVC UNDEFs if EL2 is not implemented. Move the handling of this from translate-a64.c into the pre_smc and pre_hvc helper functions. This is necessary because use of these instructions for PSCI takes precedence over this UNDEF case, and we can't tell if this is a PSCI call until runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-5-git-send-email-peter.maydell@linaro.org
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+13
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-9/+22
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-8-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell1-5/+86
Implement ARMv8 software single-step handling for A64 code: correctly update the single-step state machine and generate debug exceptions when stepping A64 code. This patch has no behavioural change since MDSCR_EL1.SS can't be set by the guest yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell1-2/+3
If gen_goto_tb() decides not to link the two TBs, then the fallback path generates unnecessary code: * if singlestep is enabled then we generate unreachable code after the gen_exception_internal(EXCP_DEBUG) * if singlestep is disabled then we will generate exit_tb(0) twice, once in gen_goto_tb() and once coming out of the main loop with is_jmp set to DISAS_JUMP Correct these deficiencies by only emitting exit_tb() in the non-singlestep case, in which case we can use DISAS_TB_JUMP to suppress the main-loop exit_tb(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Fix return address for A64 BRK instructionsPeter Maydell1-1/+1
When we take an exception resulting from a BRK instruction, the architecture requires that the "preferred return address" reported to the exception handler is the address of the BRK itself, not the following instruction (like undefined insns, and in contrast with SVC, HVC and SMC). Follow this, rather than incorrectly reporting the address of the following insn. (We do get this correct for the A32/T32 BKPT insns.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+2
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-19target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell1-1/+1
In handle_simd_shift_fpint_conv(), the combination of is_double == true, is_scalar == false and is_q == false is an unallocated encoding; the 'both parts false' case of the nested ?: expression for calculating maxpass is therefore unreachable and can be removed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1402171881-14343-4-git-send-email-peter.maydell@linaro.org
2014-06-19target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell1-1/+2
In disas_simd_3same_int(), none of the instructions permit is_q to be false with size == 3 (this would be a vector operation with a one-element vector, and the instruction set encodes those as scalar operations). Replace the always-true ?: check with an assert. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1402171881-14343-3-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell1-1/+44
Implement the two-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-10-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement 3-register SHA instructionsPeter Maydell1-1/+58
Implement the 3-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-9-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement AES instructionsPeter Maydell1-1/+50
Implement the AES instructions from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-8-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell1-1/+53
Implement the optional A64 CRC instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-6-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell1-1/+1
Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for the A64 PMULL, not the AES feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini1-0/+1
These will soon require cpu_ldst.h, so move them out of cpu.h. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-27target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias1-0/+4
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-19-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-27target-arm: Move get_mem_index to translate.hEdgar E. Iglesias1-9/+0
So that it can be shared with the AArch32 code. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-2-git-send-email-edgar.iglesias@gmail.com Message-id: 1400805738-11889-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-01target-arm: A64: Handle blr lrEdgar E. Iglesias1-1/+2
For linked branches, updates to the link register happen conceptually after the read of the branch target register. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Cc: qemu-stable@nongnu.org Message-id: 1398926097-28097-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-01target-arm: implement WFE/YIELD as a yield for AArch64Rob Herring1-0/+6
Like was done for AArch32 for WFE, implement both WFE and YIELD as a yield operation. This speeds up multi-core system emulation. Signed-off-by: Rob Herring <rob.herring@linaro.org> Message-id: 1397588401-20366-1-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée1-1/+1
The test for the U bit was incorrectly inverted in the scalar case of SQXTUN. This doesn't affect the vector case as the U bit is used to select XTN(2). Reported-by: Hao Liu <hao.liu@arm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+3
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or AArch32 EL0 are supported. Signed-off-by: Rob Herring <rob.herring@linaro.org> [PMM: fixed minor style nits; updated to match changes in previous patches; added some of the simpler cases of illegal-exception-return support] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-0/+5
Implement the DC ZVA instruction, which clears a block of memory. The fast path obtains a pointer to the underlying RAM via the TCG TLB data structure so we can do a direct memset(), with fallback to a simple byte-store loop in the slow path. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: A64: Add assertion that FP access was checkedPeter Maydell1-24/+51
Because unallocated encodings generate different exception syndrome information from traps due to FP being disabled, we can't do a single "is fp access disabled" check at a high level in the decode tree. To help in catching bugs where the access check was forgotten in some code path, we set this flag when the access check is done, and assert that it is set at the point where we actually touch the FP regs. This requires us to pass the DisasContext to the vec_reg_offset and fp_reg_offset functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN setPeter Maydell1-5/+295
For the A64 instruction set, the only FP/Neon disable trap is the CPACR FPEN bits, which may indicate "enabled", "disabled" or "disabled for EL0". Add a bit to the AArch64 tb flags indicating whether FP/Neon access is currently enabled and make the decoder emit code to raise exceptions on use of FP/Neon insns if it is not. We use a new flag in DisasContext rather than borrowing the existing vfp_enabled flag because the A32/T32 decoder is going to need both. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> --- I'm aware this is a rather hard to review patch; sorry. I have done an exhaustive check that we have fp access checks in all code paths with the aid of the assertions added in the next patch plus the code-coverage hack patch I posted to the list earlier. This patch is correct as of 09e037354 target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD) which was the last of the Neon insns to be added, so assuming no refactoring of the code it should be fine.
2014-04-17target-arm: Add support for generating exceptions with syndrome informationPeter Maydell1-14/+35
Add new helpers exception_with_syndrome (for generating an exception with syndrome information) and exception_uncategorized (for generating an exception with "Unknown or Uncategorized Reason", which have a syndrome register value of zero), and use them to generate the correct syndrome information for exceptions which are raised directly from generated code. This patch includes moving the A32/T32 gen_exception_insn functions further up in the source file; they will be needed for "VFP/Neon disabled" exception generation later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell1-1/+7
For exceptions taken to AArch64, if a coprocessor/system register access fails due to a trap or enable bit then the syndrome information must include details of the failing instruction (crn/crm/opc1/opc2 fields, etc). Make the decoder construct the syndrome information at translate time so it can be passed at runtime to the access-check helper function and used as required. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell1-0/+1
Currently cpu.h defines a mixture of functions and types needed by the rest of QEMU and those needed only by files within target-arm/. Split the latter out into a new header so they aren't needlessly exposed further than required. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-03-24target-arm: Fix A64 Neon MLSPeter Maydell1-1/+1
The order of operands for the accumulate step in disas_simd_3same_int() was reversed. This only affected the MLS instruction, since all the other accumulating instructions in this category perform an addition rather than a subtraction. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-18target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée1-4/+105
Add the saturating accumulate operations USQADD and SUQADD to the A64 instruction set. This completes coverage of A64 Neon. These operations (which are unsigned + signed -> signed and signed + unsigned -> unsigned) don't exist in the A32/T32 instruction set, so require a complete new set of helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-18target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée1-6/+45
This mostly re-uses the existing NEON helpers with an additional two for the 64 bit case. I also took the opportunity to add TCG_CALL_NO_RWG options to the helpers as they don't modify globals (saturation flags are in the CPU Environment). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée1-6/+21
This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell1-1/+19
Implement the FCVTXN operation, which does a narrowing fp precision conversion using the "round to odd" (von Neumann) mode. This can conveniently be implemented as "do operation using round to zero; then set the LSB of the mantissa to 1 if the Inexact flag was set". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-24-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement scalar saturating narrow opsAlex Bennée1-7/+28
This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Move handle_2misc_narrow functionAlex Bennée1-90/+90
Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée1-3/+19
Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell1-2/+78
Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell1-0/+132
Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-18-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FRINT*Peter Maydell1-3/+42
Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-16-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SRIPeter Maydell1-8/+49
Implement SRI (shift right and insert). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-15-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée1-1/+69
These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-14-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: List unsupported shift-imm opcodesPeter Maydell1-2/+11
Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTLPeter Maydell1-0/+47
Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-12-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTNPeter Maydell1-1/+23
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-11-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell1-19/+169
Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-10-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SHLL, SHLL2Peter Maydell1-1/+31
Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-9-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell1-1/+74
Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Saturating and narrowing shift opsAlex Bennée1-3/+178
This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are saturating and narrowing shift right operations. These are used in things like libav. Note signed shifts can have an "unsigned" saturating narrow operation which will floor negative values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-7-git-send-email-peter.maydell@linaro.org [PMM: Added the scalar encodings, style tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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