peter/qemu - QEMU hacking for Peter

Age	Commit message (Expand)	Author	Files	Lines
2013-12-17	target-arm: A64: add support for logical (immediate) insns	Alexander Graf	1	-2/+173
2013-12-17	target-arm: A64: add support for 1-src CLS insn	Claudio Fontana	1	-1/+19
2013-12-17	target-arm: A64: add support for bitfield insns	Claudio Fontana	1	-2/+54
2013-12-17	target-arm: A64: add support for 1-src REV insns	Claudio Fontana	1	-1/+72
2013-12-17	target-arm: A64: add support for 1-src RBIT insn	Alexander Graf	1	-0/+20
2013-12-17	target-arm: A64: add support for 1-src data processing and CLZ	Claudio Fontana	1	-2/+50
2013-12-17	target-arm: A64: add support for 2-src shift reg insns	Alexander Graf	1	-0/+22
2013-12-17	target-arm: A64: add support for 2-src data processing and DIV	Alexander Graf	1	-2/+70
2013-12-17	target-arm: A64: add support for EXTR	Alexander Graf	1	-2/+47
2013-12-17	target-arm: A64: add support for ADR and ADRP	Alexander Graf	1	-2/+23
2013-12-17	target-arm: A64: add support for logical (shifted register)	Alexander Graf	1	-6/+191
2013-12-17	target-arm: A64: add support for conditional select	Claudio Fontana	1	-2/+65
2013-12-17	target-arm: A64: add support for compare and branch imm	Alexander Graf	1	-2/+44
2013-12-17	target-arm: A64: add support for 'test and branch' imm	Alexander Graf	1	-2/+25
2013-12-17	target-arm: A64: add support for conditional branches	Alexander Graf	1	-2/+27
2013-12-17	target-arm: A64: add support for BR, BLR and RET insns	Alexander Graf	1	-2/+41
2013-12-17	target-arm: A64: add support for B and BL insns	Alexander Graf	1	-2/+62
2013-12-17	target-arm: A64: expand decoding skeleton for system instructions	Claudio Fontana	1	-2/+129
2013-12-17	target-arm: A64: provide skeleton for a64 insn decoding	Claudio Fontana	1	-8/+362
2013-12-17	target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()	Peter Maydell	1	-5/+204
2013-12-17	target-arm: Clean up handling of AArch64 PSTATE	Peter Maydell	1	-5/+7
2013-09-10	target-arm: Add AArch64 translation stub	Alexander Graf	1	-0/+139