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2014-02-20target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUsPeter Maydell1-1/+15
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell5-4/+130
2014-02-20target-arm: A64: Implement floating point pairwise insnsAlex Bennée1-38/+86
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée3-12/+207
2014-02-20target-arm: A64: Implement scalar three different instructionsPeter Maydell1-1/+94
2014-02-20target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell1-33/+82
2014-02-20target-arm: A64: Implement long vector x indexed insnsPeter Maydell1-5/+139
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell3-1/+275
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+2
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+2
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-6/+9
2014-02-08disas: Implement disassembly output for A64Claudio Fontana1-1/+1
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton1-22/+61
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell1-3/+20
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée1-1/+70
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell1-2/+83
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell3-6/+41
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell1-2/+134
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell1-1/+109
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell1-1/+86
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell1-19/+87
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell1-1/+113
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell1-1/+123
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell1-4/+127
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell1-22/+112
2014-01-31target-arm: A64: Add SIMD shift by immediateAlex Bennée1-2/+373
2014-01-31target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell1-2/+188
2014-01-31target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell1-1/+164
2014-01-31target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell1-1/+72
2014-01-31target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell1-1/+44
2014-01-31target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell1-1/+130
2014-01-31target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell1-2/+33
2014-01-31target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell1-1/+232
2014-01-31target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton1-1/+52
2014-01-31target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton1-0/+61
2014-01-31target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZWill Newton1-1/+39
2014-01-31target-arm: Add set_neon_rmode helperWill Newton2-0/+18
2014-01-31target-arm: Add support for AArch32 SIMD VRINTXWill Newton1-1/+10
2014-01-31target-arm: Add support for AArch32 FP VRINTXWill Newton1-0/+11
2014-01-31target-arm: Add support for AArch32 FP VRINTZWill Newton1-0/+16
2014-01-31target-arm: Add support for AArch32 FP VRINTRWill Newton1-0/+11
2014-01-31target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTMWill Newton1-0/+54
2014-01-31target-arm: Move arm_rmode_to_sf to a shared location.Will Newton3-28/+30
2014-01-31ARM: Convert MIDR to a propertyAlistair Francis1-0/+1
2014-01-31target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell1-1/+42
2014-01-31target-arm: A64: Add SIMD modified immediate groupAlex Bennée1-1/+119
2014-01-31target-arm: A64: Add SIMD copy operationsAlex Bennée1-1/+209
2014-01-31target-arm: A64: Add SIMD across-lanes instructionsMichael Matz1-1/+176
2014-01-31target-arm: A64: Add SIMD ZIP/UZP/TRNMichael Matz1-1/+75
2014-01-31target-arm: A64: Add SIMD TBL/TBLXMichael Matz3-1/+86
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