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2014-02-20target-arm: A64: Implement store-exclusive for system modePeter Maydell1-6/+62
System mode store-exclusive use a different code path to usermode ones; implement this missing code, in a similar way to the 32 bit version. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: Fix incorrect type for value argument to write_raw_cp_regPeter Maydell1-1/+1
The write_raw_cp_reg's value argument should be a uint64_t, since that's what all its callers hand it and what all the functions it calls take. A (harmless) typo meant we were accidentally declaring it as int64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Remove failure status return from read/write_raw_cp_regPeter Maydell1-24/+12
The read_raw_cp_reg and write_raw_cp_reg functions can now never fail (in fact they should never have failed previously unless there was a bug in a reginfo that meant no raw accessor was provided for a might-trap register). This allows us to clean up their prototypes so the write function returns void and the read function returns the value read, which in turn lets us simplify the callers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell2-6/+0
Now that cpreg read and write functions can't fail and throw an exception, we can remove the code from the translator that synchronises the guest PC in case an exception is thrown. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell4-208/+137
All cpreg read and write functions now return 0, so we can clean up their prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to This is a fairly mechanical change which makes only the bare minimum set of changes to the callers of read and write functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Convert miscellaneous reginfo structs to accessfnPeter Maydell1-25/+19
Convert the remaining miscellaneous cases of reginfo read/write functions returning EXCP_UDEF to use an accessfn instead: TEEHBR, and the ATS address-translation operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: Convert generic timer reginfo to accessfnPeter Maydell1-56/+66
Convert the reginfo structs for the generic timer registers to use access functions rather than returning EXCP_UDEF from their read handlers. In some cases this allows us to remove a read handler completely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Convert performance monitor reginfo to accessfnPeter Maydell1-42/+28
Convert the performance monitor reginfo definitions to use an accessfn rather than returning EXCP_UDEF from read and write functions. This also allows us to fix a couple of XXX cases where we weren't imposing the access restrictions on RAZ/WI or constant registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell5-4/+66
Several of the system registers handled via the ARMCPRegInfo mechanism have access trap control bits controlling whether the registers are accessible to lower privilege levels. Replace the existing mechanism (allowing the read and write functions to return EXCP_UDEF if access is denied) with a dedicated "check access rights" function pointer in the ARMCPRegInfo. This will allow us to simplify some of the register definitions, which no longer need read/write functions purely to handle the access checks. We take the opportunity to define the return value from the access checking function in a way that allows us to set the correct exception syndrome information for exceptions taken to AArch64 (which may need to distinguish access failures due to a configurable trap or enable from other kinds of access failure). This commit defines the new mechanism but does not move any of the registers across to use it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Stop underdecoding ARM946 PRBS registersPeter Maydell1-23/+24
The ARM946 has 8 PRBS (protection region base and size) registers. Currently we implement these with a CP_ANY reginfo; however this underdecodes (since there are 16 possible values of CRm but only 8 registers) and we catch the invalid values in the read and write functions. However this causes issues with migration since we only migrate the first of a wildcard register set, so we only migrate c6_region[0]. It also makes it awkward to pull reginfo access checks out into their own function. Avoid all these problems by just defining separate reginfo structs for each of the 8 registers; this also lets us avoid having any read or write functions and will result in more efficient direct field accesses from generated code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell2-1/+19
Log guest attempts to access unimplemented system registers via the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit instruction sets). This is particularly useful for debugging problems where the guest is trying to use a system register that QEMU doesn't implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Remove unused ARMCPUState sr substructPeter Maydell1-5/+0
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is a hangover from the original separate system register implementation used by the SuSE linux-user-mode-only AArch64 target. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Restrict check_ap() use of S and R bits to v6 and earlierPeter Maydell1-0/+3
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier. In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard the use of them in check_ap() so that we don't get incorrect results for ARMv8 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-20target-arm: Define names for SCTLR bitsPeter Maydell3-9/+61
The SCTLR is full of bits for enabling or disabling various things, and so there are many places in the code which check if certain bits are set. Define some named constants for the SCTLR bits so these checks are easier to read. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUsPeter Maydell1-1/+15
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_* constant to include all the ones currently supported by the kernel headers we are using. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell5-4/+130
Implement the remaining instructions in the SIMD 3-reg-same and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE, FACGT, FMLA and FMLS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: A64: Implement floating point pairwise insnsAlex Bennée1-38/+86
Add support for the floating-point pairwise operations FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the code which was previously handling only integer pairwise operations, and push the integer-specific decode and handling of unallocated cases up one level in the call tree, so we can also call it from the floating-point section of the decoder. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée3-12/+207
This adds all forms of the SIMD floating point and set instructions: FCM(GT|GE|EQ|LE|LT) Most of the heavy lifting is done by either the existing neon helpers or some new helpers for the 64bit double cases. Most of the code paths are common although the 2misc versions are a little special as they compare against zero. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [PMM: fixed some minor bugs, added the 2-misc-scalar encoding] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: A64: Implement scalar three different instructionsPeter Maydell1-1/+94
Implement the scalar three different instruction group: it only has three instructions in it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell1-33/+82
Implement the SIMD scalar indexed instructions. The encoding here is nearly identical to the vector indexed grouping, so we combine the two. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: A64: Implement long vector x indexed insnsPeter Maydell1-5/+139
Implement the 'long' operations in the vector x indexed element category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell3-1/+275
Implement all the SIMD vector x indexed element instructions in the subcategory which are not 'long' ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-6/+9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-08disas: Implement disassembly output for A64Claudio Fontana1-1/+1
Use libvixl to implement disassembly output in debug logs for A64, for use with both AArch64 hosts and targets. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: * added support for target disassembly * switched to custom QEMUDisassembler so the output format matches what QEMU expects * make sure we correctly fall back to "just print hex" if we didn't build the AArch64 disassembler because of lack of a C++ compiler * rename from 'aarch64' to 'arm-a64' because this is a disassembler for the A64 instruction set * merge aarch64.c and aarch64-cxx.cc into one C++ file * simplify the aarch64.c<->aarch64-cxx.cc interface] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton1-22/+61
Add support for the AArch32 floating-point half-precision to double- precision conversion VCVTB and VCVTT instructions. Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: fixed a minor missing-braces style issue] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell1-3/+20
Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée1-1/+70
Add the byte-reverse operations REV64, REV32 and REV16 from the two-reg-misc group. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell1-2/+83
Add the narrowing integer instructions in the 2-reg-misc class. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell3-6/+41
Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell1-2/+134
Implement the simple 2-register-misc operations we can share with the scalar-two-register-misc code. (SUQADD, USQADD, SQABS, SQNEG also fall into this category, but aren't implemented in the scalar-2-register case yet either.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell1-1/+109
Add a skeleton decode for the SIMD 2-reg misc group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell1-1/+86
Implement the simple 64 bit integer operations from the SIMD scalar 2-register misc group (C3.6.12): the comparisons against zero, plus ABS and NEG. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell1-19/+87
Implement the remaining integer instructions in the scalar-three-reg-same group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL, SQDMULH, SQRDMULH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell1-1/+113
Implement the instructions in the scalar pairwise group (C3.6.8). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell1-1/+123
Implement the pairwise integer operations in the 3-reg-same SIMD group: ADDP, SMAXP, SMINP, UMAXP and UMINP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell1-4/+127
Implement the SIMD 3-reg-same instructions where the size == 3 case is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX, UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL, SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.) This completes the non-pairwise integer instructions in this category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell1-22/+112
Implement the SIMD 3-reg-same instructions SQADD, UQADD, SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL, SQRSHL, UQRSHL; these are all simple calls to existing Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL for the 3-reg-same-scalar category (but not the others because they can have non-size-64 operands and the scalar_3reg_same function doesn't support that yet.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD shift by immediateAlex Bennée1-2/+373
This implements a subset of the AdvSIMD shift operations (namely all the none saturating or narrowing ones). The actual shift generation code itself is common for both the scalar and vector cases but wrapped with either vector element iteration or the fp reg access. The rounding operations need to take special care to correctly reflect the result of adding rounding bits on high bits as the intermediates do not truncate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell1-2/+188
Implement a simple subset of the SIMD 3-same floating point operations. This includes a common helper function used for both scalar and vector ops; FABD is the only currently implemented shared op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell1-1/+164
Add some of the integer operations in the SIMD 3-same group: specifically, the comparisons, addition and subtraction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell1-1/+72
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL, BIT and BIF) from the SIMD 3 register same group (C3.6.16). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell1-1/+44
Add top level decode for the A64 SIMD three regs same group (C3.6.16), splitting it into the pairwise, logical, float and integer subgroups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell1-1/+130
Implement the add, sub and compare ops from the SIMD "scalar three same" group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell1-2/+33
Implement the absolute-difference instructions in the SIMD three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL, SABDL2, UABDL, UABDL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell1-1/+232
Add support for the multiply-accumulate instructions from the SIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts * framework for handling the 64x64->128 widening subpart * implementation of the multiply-accumulate instructions SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2, UMULL, UMULL2, SMULL, SMULL2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-31target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton1-1/+52
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP and VCVTM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton1-0/+61
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP and VCVTM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZWill Newton1-1/+39
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP VRINTM and VRINTZ instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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