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2013-12-17target-arm: A64: add support for logical (immediate) insnsAlexander Graf1-2/+173
This patch adds support for C3.4.4 Logical (immediate), which include AND, ANDS, ORR, EOR. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, function renaming, removed a TCG temp variable] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: cleaned up some unnecessary code in logic_imm_decode_wmask and added clarifying commentary on what it's actually doing. Dropped an ext32u that's not needed if we've just done an AND.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src CLS insnClaudio Fontana3-1/+31
this patch adds support for the CLS instruction. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for bitfield insnsClaudio Fontana1-2/+54
This patch implements the C3.4.2 Bitfield instructions: SBFM, BFM, UBFM. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src REV insnsClaudio Fontana1-1/+72
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src RBIT insnAlexander Graf3-0/+39
This adds support for the C5.6.147 RBIT instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, splitting REV into a separate patch] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana3-2/+56
This patch adds support for decoding 1-src data processing insns, and the first user, C5.6.40 CLZ (count leading zeroes). Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 2-src shift reg insnsAlexander Graf1-0/+22
This adds 2-src variable shift register instructions: C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use enums for shift types] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 2-src data processing and DIVAlexander Graf3-2/+93
This patch adds support for decoding 2-src data processing insns, and the first users, UDIV and SDIV. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder adding the 2-src decoding level, always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for EXTRAlexander Graf1-2/+47
This patch adds emulation support for the EXTR instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more unallocated cases] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for ADR and ADRPAlexander Graf1-2/+23
Add support for the instructions described in "C3.4.6 PC-rel. addressing" (ADR and ADRP). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: A64: add support for logical (shifted register)Alexander Graf1-6/+191
Add support for the instructions described in "C3.5.10 Logical (shifted register)". We store the flags in the same locations as the 32 bit decoder. This is slightly awkward when calculating 64 bit results, but seems a better tradeoff than having to rework the whole 32 bit decoder and also make 32 bit result calculation in A64 awkward. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: some refactoring to avoid hidden allocation of temps, rework flags, use enums for shift types, renaming of functions] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for conditional selectClaudio Fontana1-2/+65
This patch adds support for the instruction group "C3.5.6 Conditional select": CSEL, CSINC, CSINV, CSNEG. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: Improved code generated in the nomatch case as per RTH suggestions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for compare and branch immAlexander Graf1-2/+44
This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 'test and branch' immAlexander Graf1-2/+25
This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for conditional branchesAlexander Graf3-7/+38
This patch adds emulation for the conditional branch (b.cond) instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf1-2/+41
Implement BR, BLR and RET. This is all of the 'unconditional branch (register)' instruction category except for ERET and DPRS (which are system mode only). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: reimplemented on top of new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for B and BL insnsAlexander Graf2-2/+65
Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the end of decode of the instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: renamed functions, adapted to new decoder layout] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana1-2/+129
Decode the various kinds of system instructions: hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL sync instructions, which include CLREX, DSB, DMB, ISB msr_i, which move immediate to processor state field sys, which include all SYS and SYSL instructions msr, which move from a gp register to a system register mrs, which move from a system register to a gp register Provide implementations where they are trivial nops. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana1-8/+362
Provide a skeleton for a64 instruction decoding in translate-a64.c, by dividing instructions into the classes defined by the ARM Architecture Reference Manual(DDI0487A_a) section C3. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf4-1/+48
We will need helpers that only make sense with AArch64. Add helper-a64.{c,h} files as stubs that we can fill with these helpers in the following patches. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: Support fp registers in gdb stubPeter Maydell1-1/+47
Register the aarch64-fpu XML and implement the necessary read/write handlers so we can support reading and writing of FP registers in the gdb stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: provide functions for accessing FPCR and FPSRPeter Maydell1-0/+28
The information which AArch32 holds in the FPSCR is split for AArch64 into two logically distinct registers, FPSR and FPCR. Since they are carefully arranged to use non-overlapping bits, we leave the underlying state in the same place, and provide accessor functions which just update the appropriate bits via vfp_get_fpscr() and vfp_set_fpscr(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add set_pc cpu methodAlexander Graf1-0/+11
When executing translation blocks we need to be able to recover our program counter. Add a method to set it for AArch64 CPUs. This covers user-mode, but for system mode emulation we will need to check if the CPU is in an AArch32 execution state. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell3-45/+246
The A32/T32 gen_intermediate_code_internal() is complicated because it has to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing None of these apply to A64, so putting the "this is A64 so call the A64 decoder" check in the middle of the A32/T32 loop is confusing and means the A64 decoder's handling of things like conditional jump and singlestepping has to take account of the conditional-execution jumps the main loop might emit. Refactor the code to give A64 its own gen_intermediate_code_internal function instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: Add minimal KVM AArch64 supportMian M. Hamayun3-0/+209
Add the bare minimum set of functions needed for control of an AArch64 KVM vcpu: * CPU initialization * minimal get/put register functions which only handle the basic state of the CPU Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-4-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled; most notably: * code lives in kvm64.c rather than using #ifdefs * support '-cpu host' rather than implicitly using whatever the host's CPU is regardless of what the user requests * fix bug attempting to get/set nonexistent X[31] * fix bug writing 64 bit kernel pstate into uint32_t env field ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2013-12-17target-arm: Clean up handling of AArch64 PSTATEPeter Maydell4-18/+74
The env->pstate field is a little odd since it doesn't strictly speaking represent an architectural register. However it's convenient for QEMU to use it to hold the various PSTATE architectural bits in the same format the architecture specifies for SPSR registers (since this is the same format the kernel uses for signal handlers and the KVM register). Add some structure to how we deal with it: * document what env->pstate is * add some #defines for various bits in it * add helpers for reading/writing it taking account of caching of NZCV, and use them where appropriate * reset it on startup Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2013-12-17target-arm/kvm: Split 32 bit only code into its own filePeter Maydell3-491/+516
Split ARM KVM support code which is 32 bit specific out into its own file, which we only compile on 32 bit hosts. This will give us a place to add the 64 bit support code without adding lots of ifdefs to kvm.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2013-12-17ARM: arm_cpu_reset: make it possible to use high vectors for reset_excAntony Pavlov1-0/+5
If hivecs are being used on reset, the CPU should come out of reset at the hivecs reset vector (0xFFFF0000) Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3afc69c4f58f60aa2bbee7b91574a4eb414b1c23.1387160489.git.peter.crosthwaite@xilinx.com [ PC Changes: * Fixed Grammar error in commit message * Elaborated commit message. ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17ARM: cpu: add "reset_hivecs" propertyAntony Pavlov2-0/+14
Add an ARM CPU property for the reset value of hivecs as it is a board/SoC configurable setting. The existence of the property is conditional on the ARM CPU not being M class. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b04216c6bda4bd163f44a55bba552d0e8267481f.1387160489.git.peter.crosthwaite@xilinx.com [ PC Changes: * Elaborated commit message * refactored to use qdev_property_add_static ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm/cpu: Convert reset CBAR to a propertyPeter Crosthwaite1-0/+17
The reset value of the CP15 CBAR is a vendor (machine) configurable property. If ARM_FEATURE_CBAR is set, add it as a property at post_init time. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2f1eec3f912135deea6252360e03645003d12e0a.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: Define and use ARM_FEATURE_CBARPeter Crosthwaite3-9/+13
Some processors (notably A9 within Highbank) define and use the CP15 configuration base address (CBAR). This is vendor specific so its best implemented as a CPU property (otherwise we would need vendor specific child classes for every ARM implementation). This patch prepares support for converting CBAR reset value to a CPU property by moving the CP registration out of the CPU init fn, as registration will need to happen at realize time to pick up any property updates. The easiest way to do this is via definition of a new ARM_FEATURE to flag the existence of the register. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 9f697ef1e2ee60a3b9ef971a7f3bc3fa6752a9b7.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm/helper.c: Allow cp15.c15 dummy overridePeter Crosthwaite1-1/+2
The cp15.c15 space is implementation defined. Currently there is a dummy placeholder register RAZing it. Allow overriding of this RAZ so implementations of specific registers can take precedence. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ed1bacec56dae00cb398c798f8240e8e685f949c.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel6-0/+313
This adds support for the AESE/AESD/AESMC/AESIMC instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: fix TTBCR write maskingSergey Fedorov1-1/+1
Current implementation is not accurate according to ARMv7-AR reference manual. See "B4.1.153 TTBCR, Translation Table Base Control Register, VMSA | TTBCR format when using the Long-descriptor translation table format". When LPAE feature is supported, EAE, bit[31] selects translation descriptor format and, therefore, TTBCR format. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386657709-23399-1-git-send-email-s.fedorov@samsung.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Use new qemu_ld/st opcodesRichard Henderson1-31/+25
Retain the existing gen_aa32_* inlines, to aid compilation for A64. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1386628626-21627-1-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.Will Newton1-9/+22
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Message-id: 1386158099-9239-7-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton3-0/+80
This adds support for the ARMv8 floating point VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 VSEL instruction.Will Newton1-1/+134
This adds support for the VSEL floating point selection instruction which was added in ARMv8. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.Will Newton1-5/+27
Floating point is an extension to the instruction set rather than a coprocessor, so call it directly from the ARM and Thumb decode functions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-2-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Provide '-cpu host' when running KVMPeter Maydell3-0/+285
Implement '-cpu host' for ARM when we're using KVM, broadly in line with other KVM-supporting architectures. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-11-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Don't hardcode KVM target CPU to be A15Peter Maydell4-1/+24
Instead of assuming that a KVM target CPU must always be a Cortex-A15 and hardcoding this in kvm_arch_init_vcpu(), store the KVM_ARM_TARGET_* value in the ARMCPU class, and use that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-10-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Allow secondary KVM CPUs to be booted via PSCIPeter Maydell3-0/+13
New ARM boards are generally expected to boot their secondary CPUs via the PSCI interface, rather than ad-hoc "loop around in holding pen code" as hw/arm/boot.c implements. In particular this is necessary for mach-virt kernels. For KVM we achieve this by creating the VCPUs with a feature flag marking them as starting in PSCI powered-down state; the guest kernel will then make a PSCI call (implemented in the host kernel) to start the secondaries at an address of its choosing once it has got the primary CPU up. Implement this setting of the feature flag, controlled by a qdev property for ARMCPU, which board code can set if it is a PSCI system. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-7-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Add ARMCPU field for Linux device-tree 'compatible' stringPeter Maydell2-0/+53
Linux requires device tree CPU nodes to include a 'compatible' string describing the CPU. Add a field in the ARMCPU struct for this so that boards which construct a device tree can insert the correct CPU nodes. Note that there is currently no officially specified 'compatible' string for the TI925T, Cortex-M3 or SA1110 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-6-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Provide PSCI constants to generic QEMU codePeter Maydell1-0/+12
Provide versions of the KVM PSCI constants to non-KVM code; this will allow us to avoid an ifdef in boards which set up a PSCI node in the device tree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-5-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVMPeter Maydell3-20/+43
There are a number of places where it would be convenient for ARM code to have working definitions of KVM constants even in code which is compiled with CONFIG_KVM not set. In this situation we can't simply include the kernel KVM headers (which might conflict with host header definitions or not even compile on the compiler we're using) so we have to redefine equivalent constants. Provide a mechanism for doing this and checking that the values match, and use it for the constants we're currently exposing via an ad-hoc mechanism. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-2-git-send-email-peter.maydell@linaro.org
2013-10-31target-arm: fix sorting issue of KVM cpreg listAlvise Rigo1-1/+7
The compare_u64 function was not sorting the KVM cpreg_list in the right way due to the wrong returned value. Since we are comparing two 64bit values we can't simply return their difference if the returned type is int. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1381513125-26802-2-git-send-email-a.rigo@virtualopensystems.com [PMM: fixed coding style, indent and commit message formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-31target-arm: sort TCG cpreg list by KVM-style 64 bit ID numberAlvise Rigo1-3/+9
Both KVM and TCG populate the cpreg_list with 64 bit register IDs, but in the TCG side the cpreg_list is sorted using the 32 bit ID version while in the kvm side the 64 bit ID version is used. This patch makes the sorting of the cpreg_list consistent between KVM and TCG. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1381513125-26802-1-git-send-email-a.rigo@virtualopensystems.com [PMM: fixed indent, coding style and commit message formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-31target-arm: Add CP15 VBAR supportNathan Rossi2-0/+22
Added Vector Base Address remapping on ARM v7. Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: removed spurious mask of value with 1<<31] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-18Merge remote-tracking branch 'bonzini/configure' into stagingAnthony Liguori1-1/+1
# By Peter Maydell (3) and Ákos Kovács (2) # Via Paolo Bonzini * bonzini/configure: ui/Makefile.objs: delete unnecessary cocoa.o dependency default-configs/: CONFIG_GDBSTUB_XML removed Makefile.target: CONFIG_NO_* variables removed rules.mak: New string testing functions rules.mak: New logical functions for handling y/n values
2013-10-16Makefile.target: CONFIG_NO_* variables removedÁkos Kovács1-1/+1
CONFIG_NO_* variables replaced with the lnot logical function Signed-off-by: Ákos Kovács <akoskovacs@gmx.com> [PMM: fixed a few CONFIG_NO_* uses that were missed] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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