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2013-07-26target-arm: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+94
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+1
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23gdbstub: Change gdb_register_coprocessor() argument to CPUStateAndreas Färber1-3/+4
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23exec: Change cpu_memory_rw_debug() argument to CPUStateAndreas Färber1-1/+1
Propagate X86CPU in kvmvapic for simplicity. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber3-4/+11
Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23gdbstub: Change syscall callback argument to CPUStateAndreas Färber1-2/+6
Callback implementations were specific to arm and m68k, so can easily cast to ARMCPU and M68kCPU respectively. Prepares for changing GDBState::c_cpu to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+8
This moves setting the Program Counter from gdbstub into target code. Use vaddr type as upper-bound replacement for target_ulong. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-15target-arm: Avoid g_hash_table_get_keys()Peter Maydell1-2/+10
g_hash_table_get_keys() was only introduced in glib 2.14, and we're still targeting a minimum version of 2.12. Rewrite the offending code (introduced in commit 721fae1) to use g_hash_table_foreach() to build the list of keys. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1372678819-8633-1-git-send-email-peter.maydell@linaro.org
2013-07-15target-arm: avoid undefined behaviour when writing TTBCRPeter Maydell1-2/+4
LPAE CPUs have more potentially valid bits in the TTBCR, and so the simple masking out of invalid bits is no longer sufficient to obtain the base address width field of the register, which is what we use to precalculate c2_mask and c2_base_mask. Explicitly extract the relevant register field rather than simply shifting by the register value. This bug would have had no ill effects in practice, since if the EAE bit (TTBCR bit 31) is set then we don't use the precalculated masks, and if EAE is zero then bits 30..3 are all UNK/SBZP, so well-behaved guests won't set them. However the shift is undefined behaviour, so we should avoid it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1372347527-4428-1-git-send-email-peter.maydell@linaro.org
2013-07-15target-arm/helper.c: Allow const opaques in arm CPPeter Crosthwaite1-1/+3
Allow for defining const opaque data in ARM CP register definitions by setting .opaque = foo. If non null opaque is passed into define_one_arm_cp_reg_with_opaque then that opaque will take precedence, otherwise if null opaque is passed, the original opaque data will be used. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: cf0a3ac3438d97464240db9f5f4ef1585cbc1d77.1373429432.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm/helper.c: Implement MIDR aliasesPeter Crosthwaite1-5/+11
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default to aliasing the MIDR register. Set all registers in the space to access MIDR by default. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 6127846712b7ad2727354a4f5e1d809451f1e859.1373429432.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanupPeter Crosthwaite1-9/+4
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo .access fields in place. So there is no need to replicate the call to define_arm_cp_reg(). Dropped, and let the OMAP case fall through to the normal behaviour after the in-place modification. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 72aae9b8ebbc9a76d2b06faf8666ef8a4b34b92a.1373429432.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm: explicitly decode SEVL instructionMans Rullgard1-1/+2
The ARMv8 SEVL instruction is in the architectural hint space already emulated as nop. This makes the decoding of SEVL explicit for clarity. Signed-off-by: Mans Rullgard <mans@mansr.com> Message-id: 1370606786-5650-3-git-send-email-mans@mansr.com [PMM: added 'SEVL' to the TODO comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm: implement LDA/STL instructionsMans Rullgard1-10/+119
This adds support for the ARMv8 load acquire/store release instructions. Since qemu does nothing special for memory barriers, these can be emulated like their non-acquire/release counterparts. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm: add feature flag for ARMv8Mans Rullgard3-1/+8
Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-09cpu: Move reset logging to CPUStateAndreas Färber1-5/+0
x86 was using additional CPU_DUMP_* flags, so make that configurable in CPUClass::reset_dump_flags. This adds reset logging for alpha, unicore32 and xtensa. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber1-1/+1
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> [AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09target-arm: Change gen_intermediate_code_internal() argument to ARMCPUAndreas Färber1-4/+5
Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber1-1/+1
A transition from CPUFooState to FooCPU can be considered safe, just like FooCPU::env access in the opposite direction. The only benefit of the FOO_CPU() casts would be protection against bogus CPUFooState pointers, but then surrounding code would likely break, too. This should slightly improve interrupt etc. performance when going from CPUFooState to FooCPU. For any additional CPU() casts see 3556c233d931ad5ffa46a35cb25cfc057732ebb8 (qom: allow turning cast debugging off). Reported-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-14/+0
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04memory: add ref/unref callsPaolo Bonzini1-0/+2
Add ref/unref calls at the following places: - places where memory regions are stashed by a listener and used outside the BQL (including in Xen or KVM). - memory_region_find callsites - creation of aliases and containers (only the aliased/contained region gets a reference to avoid loops) - around calls to del_subregion/add_subregion, where the region could disappear after the first call Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-1/+0
This allows to move the call into CPUState's realizefn. Therefore move the stub into libqemustub.a. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber4-3/+10
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-25target-arm: Make LPAE feature imply V7MPPeter Maydell1-1/+1
The v7 ARM ARM specifies that the Large Physical Address Extension requires implementation of the Multiprocessing Extensions, so make our LPAE feature imply V7MP rather than specifying both in the A15 CPU initfn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1371127899-10364-1-git-send-email-peter.maydell@linaro.org
2013-06-25target-arm: Use tuple list to sync cp regs with KVMPeter Maydell1-70/+33
Use the tuple list of cp registers for syncing KVM state to QEMU, rather than only syncing a very minimal set by hand. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Reinitialize all KVM VCPU registers on resetPeter Maydell2-1/+21
Since the ARM KVM API doesn't include a "reset this VCPU" ioctl, we have to capture the initial values of every register it knows about so that we can reset the VCPU by feeding those values back again. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Initialize cpreg list from KVM when using KVMPeter Maydell5-6/+245
When using KVM, use the kernel's initial state to set up the cpreg list, and sync to and from the kernel when doing migration. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Convert TCG to using (index,value) list for cp migrationPeter Maydell6-47/+341
Convert the TCG ARM target to using an (index,value) list for migrating coprocessors. The primary benefit of the (index,value) list is for passing state between KVM and QEMU, but it works for TCG-to-TCG migration as well and is a useful self-contained first step. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: mark up cpregs for no-migrate or raw accessPeter Maydell1-46/+94
Mark up coprocessor register definitions to add raw access functions or mark the register as non-migratable where necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfoPeter Maydell2-1/+30
For reading and writing register values from the kernel for KVM, we need to provide accessor functions which are guaranteed to succeed and don't impose access checks, mask out unwritable bits, etc. Define new fields raw_readfn and raw_writefn for this purpose; these only need to be provided if there is a readfn or writefn already and it is not suitable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-25target-arm: Allow special cpregs to have flags setPeter Maydell1-1/+1
Relax the "is this a valid ARMCPRegInfo type value?" check to permit "special" cpregs to have flags other than ARM_CP_SPECIAL set. At the moment none of the other flags are relevant for special regs, but the migration related flag we're about to introduce can apply here too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-14Merge remote-tracking branch 'mjt/trivial-patches-next' into stagingAnthony Liguori1-0/+4
# By Michael Tokarev (4) and others # Via Michael Tokarev * mjt/trivial-patches-next: (26 commits) piix: fix some printf errors when debug is enabled cputlb: fix debug logs create qemu_openpty_raw() helper function and move it to a separate file main-loop: do not include slirp/slirp.h, use libslirp.h instead libcacard/vscclient: fix leakage of socket on error paths linux-headers: Update to v3.10-rc5 KVM: PPC: Add dummy kvm_arch_init_irq_routing() KVM: S390: Add dummy kvm_arch_init_irq_routing() KVM: ARM: Add dummy kvm_arch_init_irq_routing() ivshmem: add missing error exit(2) hw/xen: Use g_free instead of free and fix potential memory leaks target-sparc: Replace free by g_free hw/scsi: Don't increment a boolean value device tree: Fix cppcheck warning Makefile: Install qemu-img and qemu-nbd man pages only if built Unbreak -no-quit for GTK, validate SDL options gtk: implement -full-screen char/serial: serial_ioport_write: Factor out common code char/serial: Use generic Fifo8 char/serial: cosmetic fixes. ... Message-id: 1371207042-17980-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-06-14Merge remote-tracking branch 'pmaydell/target-arm.next' into stagingAnthony Liguori1-1/+1
# By Peter Chubb # Via Peter Maydell * pmaydell/target-arm.next: Fix rfe instruction Message-id: 1370268884-25945-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-06-12KVM: ARM: Add dummy kvm_arch_init_irq_routing()Alexey Kardashevskiy1-0/+4
The common KVM code insists on calling kvm_arch_init_irq_routing() as soon as it sees kernel header support for it (regardless of whether QEMU supports it). Provide a dummy function to satisfy this. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-06-03Fix rfe instructionPeter Chubb1-1/+1
The rfe instruction has been broken since patch 5a839c0d54fac9db0516904db873a4fe01f50f4b because of a typo. Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-01Remove unnecessary break statementsStefan Weil1-1/+0
Fix these warnings from cppcheck: hw/display/cirrus_vga.c:2603: hw/sd/sd.c:348: hw/timer/exynos4210_mct.c:1033: target-arm/translate.c:9886: target-s390x/mem_helper.c:518: target-unicore32/translate.c:1936: style: Consecutive return, break, continue, goto or throw statements are unnecessary. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-26target-arm: Remove gen_{ld,st}* definitionsPeter Maydell1-46/+0
All the uses of the gen_{ld,st}* functions are gone now, so remove the functions themselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_{ld,st}* from thumb2 decoderPeter Maydell1-10/+20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_{ld,st}* from Thumb insnsPeter Maydell1-25/+46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_{ld,st}* from basic ARM insnsPeter Maydell1-32/+69
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove use of gen_{ld,st}* from ldrex/strexPeter Maydell1-13/+18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove uses of gen_{ld,st}* from Neon codePeter Maydell1-18/+28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove uses of gen_{ld,st}* from iWMMXt codePeter Maydell1-8/+10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_ld64() and gen_st64()Peter Maydell1-15/+4
gen_ld64() and gen_st64() are used only in one place, so just expand them out. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Don't use TCGv when we mean TCGv_i32Peter Maydell1-224/+229
TCGv changes size depending on the compile time value of TARGET_LONG_BITS. This is useful for generating code for MIPS style "instructions are the same but the register width changes" CPUs, and also for the generic bits of QEMU which operate on "width of a virtual address" values, but mostly in the ARM target code we were using it purely as a shorthand for "any 32 bit value". This needs to change in preparation for AArch64 support, since an AArch64-capable v8 core will have 64 bit virtual addresses but still use 32 bit values for the 32 bit instruction set. This patch mechanically converts all the occurrences of TCGv, tcg_temp_new(), tcg_temp_free(), tcg_temp_local_new() and TCGV_UNUSED() to their explicitly 32 bit counterparts. This is correct for everything except the arguments to tcg_gen_qemu_{ld,st}*, which really do need to be TCGv and so will require a 32-to-64 conversion when building the 32 bit code for AArch64. Those changes will be in a separate patch for easier review. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-03target-arm: Fix incorrect check of kvm_vcpu_ioctl return valuePeter Maydell1-2/+2
kvm_vcpu_ioctl() returns -ETHING on error, not ETHING -- correct an incorrect check in kvm_arch_init_vcpu(). This would not have had any significant ill-effects -- we would just have propagated the less useful ENOENT up to the caller rather than the more accurate EINVAL in the unlikely case that the kernel didn't have VFP-D32 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: Correctly restore FPSCRPeter Maydell1-7/+41
Use the helper functions to save and restore the FPSCR, so that we correctly propagate rounding mode and flushing behaviour into the float_status fields. This also allows us to stop saving the vector length/stride fields separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: Add some missing CPU state fields to VMStatePeter Maydell1-3/+10
A number of CPU state fields were accidentally omitted from our migration state: some OMAP specific cp15 registers, and some related to state for load/store exclusive insns. Add them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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