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AgeCommit message (Expand)AuthorFilesLines
2014-01-07target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell5-12/+17
2014-01-06hw: Remove assert_no_error usagesPeter Crosthwaite1-5/+2
2014-01-04target-arm: Update generic cpreg code for AArch64Peter Maydell3-9/+211
2014-01-04target-arm: Pull "add one cpreg to hashtable" into its own functionPeter Maydell1-42/+52
2013-12-23target-arm: A64: implement FMOVPeter Maydell1-1/+85
2013-12-23target-arm: A64: Add decoder skeleton for FP instructionsPeter Maydell1-1/+169
2013-12-23target-arm: A64: implement SVC, BRKAlexander Graf1-2/+49
2013-12-23target-arm: A64: add support for 3 src data proc insnsAlexander Graf1-2/+95
2013-12-23target-arm: A64: add support for move wide instructionsAlex Bennée1-2/+49
2013-12-23target-arm: A64: add support for add, addi, sub, subiAlex Bennée1-6/+286
2013-12-23target-arm: A64: add support for ld/st with indexAlex Bennée1-1/+124
2013-12-23target-arm: A64: add support for ld/st with reg offsetAlex Bennée1-1/+143
2013-12-23target-arm: A64: add support for ld/st unsigned immAlex Bennée1-1/+88
2013-12-23target-arm: A64: add support for ld/st pairPeter Maydell1-2/+277
2013-12-17target-arm: A64: add support for logical (immediate) insnsAlexander Graf1-2/+173
2013-12-17target-arm: A64: add support for 1-src CLS insnClaudio Fontana3-1/+31
2013-12-17target-arm: A64: add support for bitfield insnsClaudio Fontana1-2/+54
2013-12-17target-arm: A64: add support for 1-src REV insnsClaudio Fontana1-1/+72
2013-12-17target-arm: A64: add support for 1-src RBIT insnAlexander Graf3-0/+39
2013-12-17target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana3-2/+56
2013-12-17target-arm: A64: add support for 2-src shift reg insnsAlexander Graf1-0/+22
2013-12-17target-arm: A64: add support for 2-src data processing and DIVAlexander Graf3-2/+93
2013-12-17target-arm: A64: add support for EXTRAlexander Graf1-2/+47
2013-12-17target-arm: A64: add support for ADR and ADRPAlexander Graf1-2/+23
2013-12-17target-arm: A64: add support for logical (shifted register)Alexander Graf1-6/+191
2013-12-17target-arm: A64: add support for conditional selectClaudio Fontana1-2/+65
2013-12-17target-arm: A64: add support for compare and branch immAlexander Graf1-2/+44
2013-12-17target-arm: A64: add support for 'test and branch' immAlexander Graf1-2/+25
2013-12-17target-arm: A64: add support for conditional branchesAlexander Graf3-7/+38
2013-12-17target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf1-2/+41
2013-12-17target-arm: A64: add support for B and BL insnsAlexander Graf2-2/+65
2013-12-17target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana1-2/+129
2013-12-17target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana1-8/+362
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf4-1/+48
2013-12-17target-arm: Support fp registers in gdb stubPeter Maydell1-1/+47
2013-12-17target-arm: A64: provide functions for accessing FPCR and FPSRPeter Maydell1-0/+28
2013-12-17target-arm: A64: add set_pc cpu methodAlexander Graf1-0/+11
2013-12-17target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell3-45/+246
2013-12-17target-arm: Add minimal KVM AArch64 supportMian M. Hamayun3-0/+209
2013-12-17target-arm: Clean up handling of AArch64 PSTATEPeter Maydell4-18/+74
2013-12-17target-arm/kvm: Split 32 bit only code into its own filePeter Maydell3-491/+516
2013-12-17ARM: arm_cpu_reset: make it possible to use high vectors for reset_excAntony Pavlov1-0/+5
2013-12-17ARM: cpu: add "reset_hivecs" propertyAntony Pavlov2-0/+14
2013-12-17target-arm/cpu: Convert reset CBAR to a propertyPeter Crosthwaite1-0/+17
2013-12-17target-arm: Define and use ARM_FEATURE_CBARPeter Crosthwaite3-9/+13
2013-12-17target-arm/helper.c: Allow cp15.c15 dummy overridePeter Crosthwaite1-1/+2
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel6-0/+313
2013-12-10target-arm: fix TTBCR write maskingSergey Fedorov1-1/+1
2013-12-10target-arm: Use new qemu_ld/st opcodesRichard Henderson1-31/+25
2013-12-10target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.Will Newton1-9/+22
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