| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-02-20 | target-arm: A64: Implement store-exclusive for system mode | Peter Maydell | 1 | -6/+62 |
| 2014-02-20 | target-arm: Fix incorrect type for value argument to write_raw_cp_reg | Peter Maydell | 1 | -1/+1 |
| 2014-02-20 | target-arm: Remove failure status return from read/write_raw_cp_reg | Peter Maydell | 1 | -24/+12 |
| 2014-02-20 | target-arm: Remove unnecessary code now read/write fns can't fail | Peter Maydell | 2 | -6/+0 |
| 2014-02-20 | target-arm: Drop success/fail return from cpreg read and write functions | Peter Maydell | 4 | -208/+137 |
| 2014-02-20 | target-arm: Convert miscellaneous reginfo structs to accessfn | Peter Maydell | 1 | -25/+19 |
| 2014-02-20 | target-arm: Convert generic timer reginfo to accessfn | Peter Maydell | 1 | -56/+66 |
| 2014-02-20 | target-arm: Convert performance monitor reginfo to accessfn | Peter Maydell | 1 | -42/+28 |
| 2014-02-20 | target-arm: Split cpreg access checks out from read/write functions | Peter Maydell | 5 | -4/+66 |
| 2014-02-20 | target-arm: Stop underdecoding ARM946 PRBS registers | Peter Maydell | 1 | -23/+24 |
| 2014-02-20 | target-arm: Log bad system register accesses with LOG_UNIMP | Peter Maydell | 2 | -1/+19 |
| 2014-02-20 | target-arm: Remove unused ARMCPUState sr substruct | Peter Maydell | 1 | -5/+0 |
| 2014-02-20 | target-arm: Restrict check_ap() use of S and R bits to v6 and earlier | Peter Maydell | 1 | -0/+3 |
| 2014-02-20 | target-arm: Define names for SCTLR bits | Peter Maydell | 3 | -9/+61 |
| 2014-02-20 | target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs | Peter Maydell | 1 | -1/+15 |
| 2014-02-20 | target-arm: A64: Implement remaining 3-same instructions | Peter Maydell | 5 | -4/+130 |
| 2014-02-20 | target-arm: A64: Implement floating point pairwise insns | Alex Bennée | 1 | -38/+86 |
| 2014-02-20 | target-arm: A64: Implement SIMD FP compare and set insns | Alex Bennée | 3 | -12/+207 |
| 2014-02-20 | target-arm: A64: Implement scalar three different instructions | Peter Maydell | 1 | -1/+94 |
| 2014-02-20 | target-arm: A64: Implement SIMD scalar indexed instructions | Peter Maydell | 1 | -33/+82 |
| 2014-02-20 | target-arm: A64: Implement long vector x indexed insns | Peter Maydell | 1 | -5/+139 |
| 2014-02-20 | target-arm: A64: Implement plain vector SIMD indexed element insns | Peter Maydell | 3 | -1/+275 |
| 2014-02-11 | exec: Make stl_*_phys input an AddressSpace | Edgar E. Iglesias | 1 | -1/+2 |
| 2014-02-11 | exec: Make ldq/ldub_*_phys input an AddressSpace | Edgar E. Iglesias | 1 | -1/+2 |
| 2014-02-11 | exec: Make ldl_*_phys input an AddressSpace | Edgar E. Iglesias | 1 | -6/+9 |
| 2014-02-08 | disas: Implement disassembly output for A64 | Claudio Fontana | 1 | -1/+1 |
| 2014-02-08 | target-arm: Add support for AArch32 64bit VCVTB and VCVTT | Will Newton | 1 | -22/+61 |
| 2014-02-08 | target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group | Peter Maydell | 1 | -3/+20 |
| 2014-02-08 | target-arm: A64: Add 2-reg-misc REV* instructions | Alex Bennée | 1 | -1/+70 |
| 2014-02-08 | target-arm: A64: Add narrowing 2-reg-misc instructions | Peter Maydell | 1 | -2/+83 |
| 2014-02-08 | target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT | Peter Maydell | 3 | -6/+41 |
| 2014-02-08 | target-arm: A64: Implement 2-register misc compares, ABS, NEG | Peter Maydell | 1 | -2/+134 |
| 2014-02-08 | target-arm: A64: Add skeleton decode for SIMD 2-reg misc group | Peter Maydell | 1 | -1/+109 |
| 2014-02-08 | target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc | Peter Maydell | 1 | -1/+86 |
| 2014-02-08 | target-arm: A64: Implement remaining integer scalar-3-same insns | Peter Maydell | 1 | -19/+87 |
| 2014-02-08 | target-arm: A64: Implement scalar pairwise ops | Peter Maydell | 1 | -1/+113 |
| 2014-02-08 | target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD | Peter Maydell | 1 | -1/+123 |
| 2014-02-08 | target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns | Peter Maydell | 1 | -4/+127 |
| 2014-02-08 | target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns | Peter Maydell | 1 | -22/+112 |
| 2014-01-31 | target-arm: A64: Add SIMD shift by immediate | Alex Bennée | 1 | -2/+373 |
| 2014-01-31 | target-arm: A64: Add simple SIMD 3-same floating point ops | Peter Maydell | 1 | -2/+188 |
| 2014-01-31 | target-arm: A64: Add integer ops from SIMD 3-same group | Peter Maydell | 1 | -1/+164 |
| 2014-01-31 | target-arm: A64: Add logic ops from SIMD 3 same group | Peter Maydell | 1 | -1/+72 |
| 2014-01-31 | target-arm: A64: Add top level decode for SIMD 3-same group | Peter Maydell | 1 | -1/+44 |
| 2014-01-31 | target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops | Peter Maydell | 1 | -1/+130 |
| 2014-01-31 | target-arm: A64: Add SIMD three-different ABDL instructions | Peter Maydell | 1 | -2/+33 |
| 2014-01-31 | target-arm: A64: Add SIMD three-different multiply accumulate insns | Peter Maydell | 1 | -1/+232 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -1/+52 |
| 2014-01-31 | target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -0/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ | Will Newton | 1 | -1/+39 |
