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2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell2-52/+25
All the uses of ARM_CPUID() to vary behaviour have now been removed, so we can delete the ARM_CPUID_* macros now. The one exception is the TI915T/925T, because of its odd behaviour where the MIDR value can be changed at runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell3-100/+1
There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2-6/+14
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell2-4/+1
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert final ID registersPeter Maydell2-50/+68
Convert the final ID registers to the new cp15 scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MPIDRPeter Maydell3-22/+31
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell3-32/+33
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell3-24/+54
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=1 registersPeter Maydell3-76/+61
Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=9 registersPeter Maydell2-79/+59
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=6 registersPeter Maydell2-53/+45
Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell3-11/+74
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 VA-PA translation registersPeter Maydell1-43/+65
Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 MMU TLB controlPeter Maydell1-20/+43
Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=15 registersPeter Maydell3-117/+126
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=10 registersPeter Maydell1-6/+5
We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=13 registersPeter Maydell1-30/+31
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=2 registersPeter Maydell2-56/+33
Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MMU fault status cp15 registersPeter Maydell1-81/+107
Convert the MMU fault status and MPU access permission cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 c3 registerPeter Maydell1-6/+12
Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert generic timer cp15 regsPeter Maydell1-12/+11
Convert the (dummy) generic timer cp15 implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert performance monitor registersPeter Maydell3-149/+158
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TLS registersPeter Maydell2-58/+19
Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert WFI/barriers special cases to cp_reginfoPeter Maydell2-51/+42
Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TEECR, TEEHBR to new schemePeter Maydell3-77/+45
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert debug registers to cp_reginfoPeter Maydell2-28/+25
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Add register_cp_regs_for_features()Peter Maydell3-0/+14
Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell4-107/+1
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell7-3/+546
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Fix 11MPCore cache type register valuePeter Maydell1-1/+1
Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-0/+4
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2-0/+510
Also drop duplicate occurrence of device-hotplug.o. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-04Kill off cpu_state_reset()Andreas Färber1-5/+0
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04target-arm: Use cpu_reset() in cpu_arm_init()Andreas Färber1-1/+1
Commit 3c30dd5a68e9fee6af67cfd0d14ed7520820f36a (target-arm: Move reset handling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacing cpu_state_reset() with cpu_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-05-10target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULLPeter Maydell1-1/+9
The macro definition of cpu_init meant that if cpu_arm_init() returned NULL this wouldn't result in cpu_init() itself returning NULL. This had the effect that "-cpu foo" for some unknown CPU name 'foo' would cause ARM targets to segfault rather than generating a useful error message. Fix this by making cpu_init a simple inline function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-05-10target-arm: When setting FPSCR.QC, don't clear other FPSCR bitsMatt Craighead1-1/+1
This patch fixes a bug affecting a variety of Neon instructions, such as VQADD. Signed-off-by: Matt Craighead <mjcraighead@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-27target-arm: Make SETEND respect bswap_code (BE8) settingPeter Maydell1-4/+4
Make the SETEND instruction respect the setting of bswap_code, so that in BE8 mode we UNDEF for attempts to switch into little-endian mode and nop for attempts to stay in big-endian mode. (This is the inverse of the existing handling of SETEND in the more common little-endian setup, which we use since we don't implement the architecturally-mandated dynamic endianness switching.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-27target-arm: Move A9 config_base_address reset value to ARMCPUPeter Maydell2-3/+2
Move the A9 config_base_address cp15 register reset value to ARMCPU. This should become a QOM property so that the Highbank board can set it without having to pull in cpu-qom.h, but at least this avoids the implicit dependency on reset ordering that the previous workaround had. Cc: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-27target-arm: Change cpu_arm_init() return type to ARMCPUAndreas Färber4-7/+7
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to obtain an ARMCPU through arm_env_get_cpu() in machine init code. This requires to adjust the inclusion site of cpu-qom.h and in turn, forward-looking, to homogenize its include order. cpu_init() must still return a CPUARMState for backwards and cross-target compatibility, so adjust the cpu_init macro. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21target-arm: Move reset handling to arm_cpu_resetPeter Maydell2-99/+92
Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Drop cpu_reset_model_id()Peter Maydell1-58/+1
cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move cache ID register setup to cpu specific init fnsPeter Maydell3-11/+18
Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_resetPeter Maydell1-2/+1
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move feature register setup to per-CPU init fnsPeter Maydell3-59/+122
Move feature register value setup to per-CPU init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move iWMMXT wCID reset to cpu_state_resetPeter Maydell1-1/+4
Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Drop JTAG_ID documentationPeter Maydell1-2/+0
None of the machines in QEMU offer a JTAG debug interface, so this info was unused. Further, the PXA250 ID contradicts the February 2002 Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21target-arm: Move SCTLR reset value setup to per cpu init fnsPeter Maydell3-12/+25
Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move CTR setup to per cpu init fnsPeter Maydell3-12/+24
Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move MVFR* setup to per cpu init fnsPeter Maydell3-12/+18
Move the MVFR* VFP feature register values to ARMCPU, so they are set up by the implementation-specific instance init functions rather than in cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
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