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path: root/target-cris/translate_v10.c
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2012-03-14target-cris: Don't overuse CPUStateAndreas Färber1-13/+13
Scripted conversion: sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc] sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2011-12-12cris: Handle conditional stores on CRISv10Stefan Sandstrom1-6/+66
Signed-off-by: Stefan Sandstrom <Stefan.Sandstrom@axis.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-06-28cris: Handle opcode zeroEdgar E. Iglesias1-3/+0
It's a valid branch pc + 2. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-05-08Fix typo in comment (truely -> truly)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-01-10cris: Allow more TB chaining for crisv10Edgar E. Iglesias1-4/+6
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-10-13cris: avoid a write only variableBlue Swirl1-3/+2
Compiling with GCC 4.6.0 20100925 produced a warning: In file included from /src/qemu/target-cris/translate.c:3154:0: /src/qemu/target-cris/translate_v10.c: In function 'dec10_prep_move_m': /src/qemu/target-cris/translate_v10.c:111:22: error: variable 'rd' set but not used [-Werror=unused-but-set-variable] Fix by deleting rd, adjust the only user. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-18Replace assert(0) with abort() or cpu_abort()Blue Swirl1-7/+9
When building with -DNDEBUG, assert(0) will not stop execution so it must not be used for abnormal termination. Use cpu_abort() when in CPU context, abort() otherwise. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-07Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
See also 8167ee883931cb20c6264fc19d040ce2dc6ceaaa, 530e7615ce3c01882e582c84dc6304ab98a3d5c5 and fad6cb1a565bb73f83fc0e2654489457b489e436. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20cris: Mask interrupts on dslots for CRISv10.Edgar E. Iglesias1-0/+4
CRISv10 cores (unlike v32) do not take any interrupts while delayed jumps are pending (delay slots). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-02-15crisv10: Prettify.Edgar E. Iglesias1-95/+91
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-02-15cris: Add support for CRISv10 translation.Edgar E. Iglesias1-0/+1243
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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