summaryrefslogtreecommitdiff
path: root/target-i386/translate.c
AgeCommit message (Collapse)AuthorFilesLines
2014-01-07target-i386: Stop encoding DisasContext.mem_indexRichard Henderson1-42/+25
Now that we don't combine mem_index with operand size info, we don't need to encode it. Which tidies many places that access it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Push DisasContext into load/store helpersRichard Henderson1-161/+170
Rather than add s->mem_index into a combined size+mem_index argument, pass the context down. This will allow cleaning up s->mem_index later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-21target-i386: Fix addr32 prefix in gen_lea_modrmRichard Henderson1-45/+47
Fix the following run-test-x86_64 testsuite failures: -lea (%%eax) = 0000000000000001 -lea (%%ebx) = 0000000000000002 -lea (%%ecx) = 0000000000000004 -lea (%%edx) = 0000000000000008 -lea (%%esi) = 0000000000000010 -lea (%%edi) = 0000000000000020 +lea (%%eax) = 0000abcc00000001 +lea (%%ebx) = 0000abcf00000002 +lea (%%ecx) = 0000abc900000004 +lea (%%edx) = 0000abc500000008 +lea (%%esi) = 0000abdd00000010 +lea (%%edi) = 0000abed00000020 In addition, reduce ifdeffery and minimize the number of TCG ops produced during address computation. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1384219016-5170-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21target-i386: yield to another VCPU on PAUSEPaolo Bonzini1-1/+4
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown. The problem shows up as soon as FreeBSD turns out its periodic (~1 ms) tick, but the timers are only the trigger for a pre-existing problem. Before the offending patch, setting a timer did a timer_settime system call. After, setting the timer exits the event loop (which uses poll) and reenters it with a new deadline. This does not cause any slowdown; the difference is between one system call (timer_settime and a signal delivery (SIGALRM) before the patch, and two system calls afterwards (write to a pipe or eventfd + calling poll again when re-entering the event loop). Unfortunately, the exit/enter causes the main loop to grab the iothread lock, which in turns kicks the VCPU thread out of execution. This causes TCG to execute the next VCPU in its round-robin scheduling of VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause" instruction in its idle loop which only burns cycles without any progress. As soon as the timer tick expires, the first VCPU runs the interrupt handler but very soon it sets it again---and QEMU then goes back doing nothing in the second VCPU. The fix is to make the pause instruction do "cpu_loop_exit". Cc: Richard Henderson <rth@twiddle.net> Reported-by: Luigi Rizzo <rizzo@iet.unipi.it> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-12target-i386: Only provide CMOV and friends if feature bit setPeter Maydell1-0/+19
The instructions CMOVcc, FCMOVcc and F[U]COMI[P] should only be present if the CMOV feature bit is set. Add missing feature bit checks so we correctly fault if emulating a 486 or 586. This fixes bug LP:1201446. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09target-i386: Change gen_intermediate_code_internal() argument to X86CPUAndreas Färber1-4/+5
Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-31target-i386: Fix aflag logic for CODE64 and the 0x67 prefixRichard Henderson1-15/+15
The code reorganization in commit 4a6fd938 broke handling of PREFIX_ADR. While fixing this, tidy and comment the code so that it's more obvious what's going on in setting both aflag and dflag. The TARGET_X86_64 ifdef can be eliminated because CODE64 expands to the constant zero when TARGET_X86_64 is undefined. Cc: Paolo Bonzini <pbonzini@redhat.com> Reported-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1369855851-21400-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-05-10target-i386: ROR r8/r16 imm instruction fixAurelien Jarno1-0/+1
Fix EFLAGS corruption by ROR r8/r16 imm instruction located at the end of the TB, similarly to commit 089305ac for the non-immediate case. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-02target-i386: Replace cpuid_*features fields with a feature word arrayEduardo Habkost1-5/+5
This replaces the feature-bit fields on both X86CPU and x86_def_t structs with an array. With this, we will be able to simplify code that simply does the same operation on all feature words (e.g. kvm_check_features_against_host(), filter_features_for_kvm(), add_flagname_to_bitmaps(), CPU feature-bit property lookup/registration, and the proposed "feature-words" property) The following field replacements were made on X86CPU and x86_def_t: (cpuid_)features -> features[FEAT_1_EDX] (cpuid_)ext_features -> features[FEAT_1_ECX] (cpuid_)ext2_features -> features[FEAT_8000_0001_EDX] (cpuid_)ext3_features -> features[FEAT_8000_0001_ECX] (cpuid_)ext4_features -> features[FEAT_C000_0001_EDX] (cpuid_)kvm_features -> features[FEAT_KVM] (cpuid_)svm_features -> features[FEAT_SVM] (cpuid_)7_0_ebx_features -> features[FEAT_7_0_EBX] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-04-20i386 ROR r8/r16 instruction fixPavel Dovgaluk1-0/+1
Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the TB. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-13target-i386: add AES-NI instructionsAurelien Jarno1-0/+7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-13target-i386: add pclmulqdq instructionAurelien Jarno1-0/+3
Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.1: fix pinsrb instructionAurelien Jarno1-2/+2
gen_op_mov_TN_reg() loads the value in cpu_T[0], so this temporary should be used instead of cpu_tmp0. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-23target-i386: Fix flags computation for ADOXRichard Henderson1-1/+1
When starting from CC_OP_DYNAMIC, and issuing adox before adcx, a typo used the wrong value for the resulting CC_OP. Cc: Blue Swirl <blauwirbel@gmail.com> Reported-by: Torbjorn Granlund <tg@gmplib.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-22Fix typos and misspellingsPeter Maydell1-1/+1
Fix various typos and misspellings. The bulk of these were found with codespell. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-27target-i386: Use mulu2 and muls2Richard Henderson1-111/+56
These correspond very closely to the insns that we're emulating. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-i386: Use add2 to implement the ADX extensionRichard Henderson1-11/+9
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-19target-i386: Use movcond to implement shiftd.Richard Henderson1-141/+106
With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Discard CC_OP computation in set_cc_op alsoRichard Henderson1-3/+11
The shift and rotate insns use movcond to set CC_OP, and thus achieve a conditional EFLAGS setting. By discarding CC_OP in a later flags setting insn, we can discard that movcond. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Use movcond to implement rotate flags.Richard Henderson1-116/+121
With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Use movcond to implement shift flags.Richard Henderson1-52/+42
With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Add CC_OP_CLRRichard Henderson1-3/+14
Special case xor with self. We need not even store the known zero into cc_src. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Implement tzcnt and fix lzcntRichard Henderson1-37/+49
We weren't computing flags for lzcnt at all. At the same time, adjust the implementation of bsf/bsr to avoid the local branch, using movcond instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Implement ADX extensionRichard Henderson1-3/+106
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement RORXRichard Henderson1-0/+32
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement SHLX, SARX, SHRXRichard Henderson1-0/+31
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement PDEP, PEXTRichard Henderson1-0/+36
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement MULXRichard Henderson1-0/+39
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement BZHIRichard Henderson1-0/+27
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement BLSR, BLSMSK, BLSIRichard Henderson1-0/+48
Do all of group 17 at one time for ease. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement BEXTRRichard Henderson1-0/+40
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement ANDNRichard Henderson1-2/+17
As this is the first of the BMI insns to be implemented, this carries quite a bit more baggage than normal. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Implement MOVBERichard Henderson1-25/+97
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Decode the VEX prefixesRichard Henderson1-4/+64
No actual required uses of these encodings yet. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Tidy prefix parsingRichard Henderson1-82/+52
Avoid duplicating switch statement between 32 and 64-bit modes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Use CC_SRC2 for ADC and SBBRichard Henderson1-49/+31
Add another slot in ENV and store two of the three inputs. This lets us do less work when carry-out is not needed, and avoids the unpredictable CC_OP after translating these insns. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Make helper_cc_compute_{all,c} constRichard Henderson1-4/+27
Pass the data in explicitly, rather than indirectly via env. This avoids all sorts of unnecessary register spillage. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: optimize flags checking after sub using CC_SRCTRichard Henderson1-15/+31
After a comparison or subtraction, the original value of the LHS will currently be reconstructed using an addition. However, in most cases it is already available: store it in a temp-local variable and save 1 or 2 TCG ops (2 if the result of the addition needs to be extended). The temp-local can be declared dead as soon as the cc_op changes again, or also before the translation block ends because gen_prepare_cc will always make a copy before returning it. All this magic, plus copy propagation and dead-code elimination, ensures that the temp local will (almost) never be spilled. Example (cmp $0x21,%rax + jbe): Before After ---------------------------------------------------------------------------- movi_i64 tmp1,$0x21 movi_i64 tmp1,$0x21 movi_i64 cc_src,$0x21 movi_i64 cc_src,$0x21 sub_i64 cc_dst,rax,tmp1 sub_i64 cc_dst,rax,tmp1 add_i64 tmp7,cc_dst,cc_src movi_i32 cc_op,$0x11 movi_i32 cc_op,$0x11 brcond_i64 tmp7,cc_src,leu,$0x0 discard loc11 brcond_i64 rax,cc_src,leu,$0x0 Before After ---------------------------------------------------------------------------- mov (%r14),%rbp mov (%r14),%rbp mov %rbp,%rbx mov %rbp,%rbx sub $0x21,%rbx sub $0x21,%rbx lea 0x21(%rbx),%r12 movl $0x11,0xa0(%r14) movl $0x11,0xa0(%r14) movq $0x21,0x90(%r14) movq $0x21,0x90(%r14) mov %rbx,0x98(%r14) mov %rbx,0x98(%r14) cmp $0x21,%r12 | cmp $0x21,%rbp jbe ... jbe ... Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: Update cc_op before TCG branchesRichard Henderson1-4/+4
Placing the CC_OP_DYNAMIC at the join is less effective than before the branch, as the branch will have forced global registers to their home locations. This way we have a chance to discard CC_SRC2 before it gets stored. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: introduce gen_jcc1_noeobRichard Henderson1-5/+22
A jump that ends a basic block or otherwise falls back to CC_OP_DYNAMIC will always have to call gen_op_set_cc_op. However, not all jumps end a basic block, so introduce a variant that does not do this. This was partially undone earlier (i386: drop cc_op argument of gen_jcc1), redo it now also to prepare for the introduction of src2. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: use gen_op for cmps/scasRichard Henderson1-14/+6
Replace low-level ops with a higher-level "cmp %al, (A0)" in the case of scas, and "cmp T0, (A0)" in the case of cmps. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: kill cpu_T3Paolo Bonzini1-11/+8
It is almost unused, and it is simpler to pass a TCG value directly to gen_shiftd_rm_T1_T3. This value is then written to t2 without going through a temporary register. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: expand cmov via movcondRichard Henderson1-25/+20
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: introduce gen_cmovcc1Paolo Bonzini1-34/+38
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: cleanup temporary macros for CCPreparePaolo Bonzini1-47/+39
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18target-i386: inline gen_prepare_cc_slowRichard Henderson1-45/+46
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-15 12:57:42 +0000