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2012-05-30Expose CPUID leaf 7 only for -cpu hostEduardo Habkost2-7/+17
Changes v2 -> v3; - Check for kvm_enabled() before setting cpuid_7_0_ebx_features Changes v1 -> v2: - Use kvm_arch_get_supported_cpuid() instead of host_cpuid() on cpu_x86_fill_host(). We should use GET_SUPPORTED_CPUID for all bits on "-cpu host" eventually, but I am not changing all the other CPUID leaves because we may not be able to test such an intrusive change in time for 1.1. Description of the bug: Since QEMU 0.15, the CPUID information on CPUID[EAX=7,ECX=0] is being returned unfiltered to the guest, directly from the GET_SUPPORTED_CPUID return value. The problem is that this makes the resulting CPU feature flags unpredictable and dependent on the host CPU and kernel version. This breaks live-migration badly if migrating from a host CPU that supports some features on that CPUID leaf (running a recent kernel) to a kernel or host CPU that doesn't support it. Migration also is incorrect (the virtual CPU changes under the guest's feet) if you migrate in the opposite direction (from an old CPU/kernel to a new CPU/kernel), but with less serious consequences (guests normally query CPUID information only once on boot). Fortunately, the bug affects only users using cpudefs with level >= 7. The right behavior should be to explicitly enable those features on [cpudef] config sections or on the "-cpu" command-line arguments. Right now there is no predefined CPU model on QEMU that has those features: the latest Intel model we have is Sandy Bridge. I would like to get this fixed on 1.1, so I am submitting this patch, that enables those features only if "-cpu host" is being used (as we don't have any pre-defined CPU model that actually have those features). After 1.1 is released, we can make those features properly configurable on [cpudef] and -cpu configuration. One problem is: with this patch, users with the following setup: - Running QEMU 1.0; - Using a cpudef having level >= 7; - Running a kernel that supports the features on CPUID leaf 7; and - Running on a CPU that supports some features on CPUID leaf 7 won't be able to live-migrate to QEMU 1.1. But for these users live-migration is already broken (they can't live-migrate to hosts with older CPUs or older kernels, already), I don't see how to avoid this problem. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-05-12target-i386: Defer MCE initAndreas Färber3-2/+13
Commit de024815e3b523addf58f1f79846b7fe74643678 (target-i386: QOM'ify CPU init) moved mce_init() call from helper.c:cpu_x86_init() into X86CPU's cpu.c:x86_cpu_initfn(). mce_init() checks for a family >= 6 though, so we could end up with a sequence such as for -cpu somecpu,family=6: x86_cpu_initfn => X86CPU::family == 5 mce_init => no-op cpu_x86_register => X86CPU::family = 6 => MCE unexpectedly not init'ed or for -cpu someothercpu,family=5: x86_cpu_initfn => X86CPU::family == 6 mce_init => init'ed cpu_x86_register => X86CPU::family = 5 => MCE unexpectedly init'ed Therefore partially revert the above commit. To avoid moving mce_init() back into helper.c, foresightedly move it into a new x86_cpu_realize() function and, in lack of ObjectClass::realize, call it directly from cpu_x86_init(). While at it, move the qemu_init_vcpu() call that used to follow mce_init() in cpu_x86_init() into the new realizefn as well. Reported-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Introduce "tsc-frequency" property for X86CPUAndreas Färber1-1/+36
Use Hz as unit. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Prepare "vendor" property for X86CPUAndreas Färber1-0/+44
Using it now would incur converting the three x86_def_t vendor words into a string for object_property_set_str(), then back to three words in the "vendor" setter. The built-in CPU definitions use numeric preprocessor defines to initialize the three words in a charset-safe way, so do not change the fields to char[12] just to use the setter. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Introduce "xlevel" property for X86CPUAndreas Färber1-1/+37
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Introduce "level" property for X86CPUAndreas Färber1-1/+37
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add property getter for CPU model-idAndreas Färber1-1/+16
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add property getter for CPU steppingAndreas Färber1-1/+13
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add property getter for CPU modelAndreas Färber1-1/+13
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2012-04-25target-i386: Add property getter for CPU familyAndreas Färber1-1/+15
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add "model-id" property to X86CPUAndreas Färber1-2/+8
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add "stepping" property to X86CPUAndreas Färber1-3/+24
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add "model" property to X86CPUAndreas Färber1-3/+23
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add "family" property to X86CPUAndreas Färber1-5/+34
Add the property early in the initfn so that it can be used in helpers such as mce_init(). Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [AF: Add an error_free(), spotted by Michael Roth] Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Add range check for -cpu ,family=xAndreas Färber1-1/+1
A family field value of 0xf and extended family field value of 0xff is the maximum representable unsigned family number. All other CPUID property values are bounds-checked, so add a check here for symmetry before we adopt it in a property setter. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Pass X86CPU to cpu_x86_register()Andreas Färber3-3/+4
Avoids an x86_env_get_cpu() call there, to work with QOM properties. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2012-04-25target-i386: Fix x86_cpuid_set_model_id()Andreas Färber1-0/+1
Don't assume zeroed cpuid_model[] fields. This didn't break anything yet but QOM properties should be able to set the value to something else without setting an intermediate zero string. Reviewed-by: Eduardo Habhost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [AF: Use memset() instead of for loop, suggested by Igor] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-5/+3
Use uintptr_t instead of void * or unsigned long in several op related functions, env->mem_io_pc and GETPC() macro. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-10target-i386: QOM'ify CPU resetAndreas Färber2-71/+72
Move code from cpu_state_reset() into QOM x86_cpu_reset(), fixing style issues for FPU init. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-10target-i386: QOM'ify CPU initAndreas Färber2-18/+27
Move code from cpu_x86_init() to new QOM x86_cpu_initfn(). Also move mce_init() to cpu.c since it's used nowhere else. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-10target-i386: QOM'ify CPUAndreas Färber4-8/+118
Embed CPUX86State as first member of X86CPU. Distinguish between "x86_64-cpu" and "i386-cpu". Drop cpu_x86_close() in favor of calling object_delete() directly. For now let CPUClass::reset() call cpu_state_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-10target-i386: Rename cpuid.cAndreas Färber1-0/+0
Name it cpu.c to align with other QOM'ified targets. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-i386: Don't overuse CPUStateAndreas Färber6-222/+222
Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber1-2/+2
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-12add "tsc-deadline" flag name to feature_ecx tableEduardo Habkost1-1/+1
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-11target-i386: Mask NX bit from cpu_get_phys_page_debug resultJan Kiszka2-6/+8
This was a long pending bug, now revealed by the assert in phys_page_find that stumbled over the large page index returned by cpu_get_phys_page_debug for NX-marked pages: We need to mask out NX and all user-definable bits 52..62 from PDEs and the final PTE to avoid corrupting physical addresses. Reviewed-by: Avi Kivity <avi@redhat.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-07kvm: fill in padding to help valgrindMichael S. Tsirkin1-0/+6
valgrind warns about padding fields which are passed to vcpu ioctls uninitialized. This is not an error in practice because kvm ignored padding. Since the ioctls in question are off data path and the cost is zero anyway, initialize padding to 0 to suppress these errors. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl2-7/+0
* 'upstream' of git://qemu.weilnetz.de/qemu: Move definition of HOST_LONG_BITS to qemu-common.h target-xtensa: Clean includes target-unicore32: Clean includes target-sh4: Clean includes target-s390x: Clean includes target-ppc: Clean includes target-mips: Clean includes target-microblaze: Clean includes target-m68k: Clean includes target-lm32: Clean includes target-i386: Clean includes target-cris: Clean includes target-arm: Clean includes target-alpha: Clean includes Remove macro HOST_LONG_SIZE
2012-03-01Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori3-2/+50
* qemu-kvm/uq/master: pc-bios: update kvmvapic.bin kvmvapic: Use optionrom helpers optionsrom: Reserve space for checksum kvmvapic: Simplify mp/up_set_tpr kvmvapic: Introduce TPR access optimization for Windows guests kvmvapic: Add option ROM target-i386: Add infrastructure for reporting TPR MMIO accesses Allow to use pause_all_vcpus from VCPU context Process pending work while waiting for initial kick-off in TCG mode Remove useless casts from cpu iterators kvm: Set cpu_single_env only once kvm: Synchronize cpu state in kvm_arch_stop_on_emulation_error()
2012-02-28target-i386: Clean includesStefan Weil2-7/+0
Remove some include statements which are not needed. Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-24target-i386: Introduce x86_cpuid_set_model_id()Andreas Färber1-14/+19
Move the logic to transform the 48-char model ID into the 12-word model value into a helper. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-24target-i386: Introduce x86_cpuid_version_set_stepping()Andreas Färber1-1/+7
Move the logic for setting the stepping field into a helper function. To make the function self-contained and to prepare for future unordered/multiple uses, mask out any previous stepping values first. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-24target-i386: Introduce x86_cpuid_version_set_model()Andreas Färber1-1/+7
Move the logic for setting the model and extended model fields into a helper function. To make the function self-contained and to prepare for future unordered/multiple uses, mask out any previous model values first. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-24target-i386: Introduce x86_cpuid_version_set_family()Andreas Färber1-4/+11
Move the logic for setting the family and extended family into a helper function. To make the helper self-contained and in preparation of future unordered/multiple uses, mask out any previous family values first. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22cpu defs: use Intel flag names for Intel models (v2)Eduardo Habkost1-2/+2
Use 'i64' instead of 'lm' and 'xd' instead of 'nx' on Intel models. The flags have different names on Intel docs, so use those names for clarity. This is based on a previous patch from John Cooper where this was introduced with many other changes at the same time. Original John's patch submission is at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>. Changes v1 -> v2: - Rebase patch against latest Qemu git tree Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-22cpu flags: aliases: pclmuldq|pclmulqdq and ffxsr|fxsr_optEduardo Habkost1-2/+2
pclmulqdq: /proc/cpuinfo on Linux and all documentation I have seen uses pclmulqdq as the flag name. As the only document using pclmuldq seems to be the Intel CPUID documentation (Application Note 485), it looks like a typo and not the correct name for the flag. ffxsr: AMD docs refer to fxsr_opt as ffxsr, so allow this named to be used too. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-18target-i386: Add infrastructure for reporting TPR MMIO accessesJan Kiszka3-2/+49
This will allow the APIC core to file a TPR access report. Depending on the accelerator and kernel irqchip mode, it will either be delivered right away or queued for later reporting. In TCG mode, we can restart the triggering instruction and can therefore forward the event directly. KVM does not allows us to restart, so we postpone the delivery of events recording in the user space APIC until the current instruction is completed. Note that KVM without in-kernel irqchip will report the address after the instruction that triggered the access. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2012-02-16kvm: Synchronize cpu state in kvm_arch_stop_on_emulation_error()Gleb Natapov1-0/+1
Call to kvm_cpu_synchronize_state() is missing. kvm_arch_stop_on_emulation_error may look at outdated registers here. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com> Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-02-08kvm: Implement kvm_irqchip_in_kernel like kvm_enabledJan Kiszka1-2/+2
To both avoid that kvm_irqchip_in_kernel always has to be paired with kvm_enabled and that the former ends up in a function call, implement it like the latter. This means keeping the state in a global variable and defining kvm_irqchip_in_kernel as a preprocessor macro. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-02-08kvm: Allow to set shadow MMU sizeJan Kiszka1-0/+13
Introduce the KVM-specific machine option kvm_shadow_mem. It allows to set a custom shadow MMU size for the virtual machine. This is useful for stress testing e.g. Only x86 supports this for now, but it is in principle a generic concept for all targets with shadow MMUs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-01-23hyperv: fix build on non-KVM hostsBlue Swirl1-1/+3
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-01-19kvm: x86: Add user space part for in-kernel APICJan Kiszka1-0/+38
This introduces the alternative APIC device which makes use of KVM's in-kernel device model. External NMI injection via LINT1 is emulated by checking the current state of the in-kernel APIC, only injecting a NMI into the VCPU if LINT1 is unmasked and configured to DM_NMI. MSI is not yet supported, so we disable this when the in-kernel model is in use. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19kvm: Introduce core services for in-kernel irqchip supportJan Kiszka1-0/+11
Add the basic infrastructure to active in-kernel irqchip support, inject interrupts into these models, and maintain IRQ routes. Routing is optional and depends on the host arch supporting KVM_CAP_IRQ_ROUTING. When it's not available on x86, we looe the HPET as we can't route GSI0 to IOAPIC pin 2. In-kernel irqchip support will once be controlled by the machine property 'kernel_irqchip', but this is not yet wired up. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19hyper-v: initialize Hyper-V CPUID leaves.Vadim Rozenfeld1-2/+63
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-01-19hyper-v: introduce Hyper-V support infrastructure.Vadim Rozenfeld3-0/+121
[Jan: fix build with CONFIG_USER_ONLY] Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2012-01-13target-i386: fix compilation with --enable-debug-tcgAurelien Jarno1-1/+2
Commit 2355c16e74ffa4d14e7fc2b4a23b055565ac0221 introduced a new ldmxcsr helper taking an i32 argument, but the helper is actually passed a long. Fix that by truncating the long to i32. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11target-i386: fix SSE rounding and flush to zeroAurelien Jarno3-11/+56
SSE rounding and flush to zero control has never been implemented. However given that softfloat-native was using a single state for FPU and SSE and given that glibc is setting both FPU and SSE state in fesetround(), this was working correctly up to the switch to softfloat. Fix that by adding an update_sse_status() function similar to update_fpu_status(), and callin git on write to mxcsr. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11target-i386: fix dpps and dppd SSE2 instructionsAurelien Jarno1-14/+14
The helpers implemented dpps and dppd SSE instructions are not passing the correct argument types to the softfloat functions. While they do work anyway providing a correct behaviour, this patch fixes that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11target-i386: fix round{pd,ps,sd,ss} SSE2 instructionsAurelien Jarno1-8/+8
roundps and roundss SSE2 instructions have been broken when switching target-i386 to softfloat. They use float64_round_to_int to convert a float32, and while the implicit conversion from float32 to float64 was correct for softfloat-native, it is not for pure softfloat. Fix that by using the correct registers and correct functions. Also fix roundpd and roundsd implementation at the same time, even if these functions are behaving correctly. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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