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2015-06-22Include qapi/qmp/qerror.h exactly where neededMarkus Armbruster1-1/+0
In particular, don't include it into headers. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>
2015-06-22qerror: Move #include out of qerror.hMarkus Armbruster1-0/+1
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>
2015-06-22qerror: Clean up QERR_ macros to expand into a single stringMarkus Armbruster1-10/+9
These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. Clean up as follows: * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-06-12migration: Use normal VMStateDescriptions for SubsectionsJuan Quintela1-49/+32
We create optional sections with this patch. But we already have optional subsections. Instead of having two mechanism that do the same, we can just generalize it. For subsections we just change: - Add a needed function to VMStateDescription - Remove VMStateSubsection (after removal of the needed function it is just a VMStateDescription) - Adjust the whole tree, moving the needed function to the corresponding VMStateDescription Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-06-05target-i386: use memory API to implement SMRAMPaolo Bonzini5-6/+51
Remove cpu_smm_register and cpu_smm_update. Instead, each CPU address space gets an extra region which is an alias of /machine/smram. This extra region is enabled or disabled as the CPU enters/exits SMM. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: create a separate AddressSpace for each CPUPaolo Bonzini2-0/+15
Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: wake up processors that receive an SMIPaolo Bonzini1-1/+3
An SMI should definitely wake up a processor in halted state! This lets OVMF boot with SMM on multiprocessor systems, although it halts very soon after that with a "CpuIndex != BspIndex" assertion failure. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: set G=1 in SMM big real mode selectorsPaolo Bonzini1-6/+6
Because the limit field's bits 31:20 is 1, G should be 1. VMX actually enforces this, let's do it for completeness in QEMU as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: mask NMIs on entry to SMMPaolo Bonzini2-9/+20
QEMU is not blocking NMIs on entry to SMM. Implementing this has to cover a few corner cases, because: - NMIs can then be enabled by an IRET instruction and there is no mechanism to _set_ the "NMIs masked" flag on exit from SMM: "A special case can occur if an SMI handler nests inside an NMI handler and then another NMI occurs. [...] When the processor enters SMM while executing an NMI handler, the processor saves the SMRAM state save map but does not save the attribute to keep NMI interrupts disabled. - However, there is some hidden state, because "If NMIs were blocked before the SMI occurred [and no IRET is executed while in SMM], they are blocked after execution of RSM." This is represented by the new HF2_SMM_INSIDE_NMI_MASK bit. If it is zero, NMIs are _unblocked_ on exit from RSM. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: Use correct memory attributes for ioport accessesPaolo Bonzini5-87/+58
In order to do this, stop using the cpu_in*/out* helpers, and instead access address_space_io directly. cpu_in* and cpu_out* remain for usage in the monitor, in qtest, and in Xen. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: Use correct memory attributes for memory accessesPaolo Bonzini5-290/+394
These include page table walks, SVM accesses and SMM state save accesses. The bulk of the patch is obtained with sed -i 's/\(\<[a-z_]*_phys\(_notdirty\)\?\>(cs\)->as,/x86_\1,/' Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-05target-i386: introduce cpu_get_mem_attrsPaolo Bonzini3-2/+8
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-04Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell2-1/+123
staging X86 queue 2015-06-02 # gpg: Signature made Tue Jun 2 20:21:17 2015 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: arch_init: Drop target-x86_64.conf target-i386: Register QOM properties for feature flags apic: convert ->busdev.qdev casts to C casts target-i386: Fix signedness of MSR_IA32_APICBASE_BASE pc: Ensure non-zero CPU ref count after attaching to ICC bus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-i386: Register QOM properties for feature flagsEduardo Habkost1-0/+122
This uses the feature name arrays to register QOM properties for feature flags. This simply adds properties that can be configured using -global, but doesn't change x86_cpu_parse_featurestr() to use them yet. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-06-02target-i386: Fix signedness of MSR_IA32_APICBASE_BASEEduardo Habkost1-1/+1
Existing definition triggers the following when using clang -fsanitize=undefined: hw/intc/apic_common.c:314:55: runtime error: left shift of 1048575 by 12 places cannot be represented in type 'int' Fix it so we won't try to shift a 1 to the sign bit of a signed integer. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-06-02kvm: introduce kvm_arch_msi_data_to_gsiEric Auger1-0/+5
On ARM the MSI data corresponds to the shared peripheral interrupt (SPI) ID. This latter equals to the SPI index + 32. to retrieve the SPI index, matching the gsi, an architecture specific function is introduced. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-30kvm: add support for memory transaction attributesPaolo Bonzini1-1/+3
Let kvm_arch_post_run convert fields in the kvm_run struct to MemTxAttrs. These are then passed to address_space_rw. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-28Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell1-46/+4
staging X86 queue, 2015-04-27 (v2) # gpg: Signature made Mon Apr 27 19:42:39 2015 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: target-i386: Remove AMD feature flag aliases from CPU model table target-i386: X86CPU::xlevel2 QOM property target-i386: Make "level" and "xlevel" properties static qemu-config: Accept empty option values MAINTAINERS: Change status of X86 to Maintained MAINTAINERS: Add myself to X86 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-27target-i386: Remove AMD feature flag aliases from CPU model tableEduardo Habkost1-7/+0
When CPU vendor is AMD, the AMD feature alias bits on CPUID[0x80000001].EDX are already automatically copied from CPUID[1].EDX on x86_cpu_realizefn(). When CPU vendor is Intel, those bits are reserved and should be zero. On either case, those bits shouldn't be set in the CPU model table. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-04-27target-i386: X86CPU::xlevel2 QOM propertyEduardo Habkost1-1/+2
We already have "level" and "xlevel", only "xlevel2" is missing. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-04-27target-i386: Make "level" and "xlevel" properties staticEduardo Habkost1-38/+2
Static properties require only 1 line of code, much simpler than the existing code that requires writing new getters/setters. As a nice side-effect, this fixes an existing bug where the setters were incorrectly allowing the properties to be changed after the CPU was already realized. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-04-26Switch non-CPU callers from ld/st*_phys to address_space_ld/st*Peter Maydell1-7/+8
Switch all the uses of ld/st*_phys to address_space_ld/st*, except for those cases where the address space is the CPU's (ie cs->as). This was done with the following script which generates a Coccinelle patch. A few over-80-columns lines in the result were rewrapped by hand where Coccinelle failed to do the wrapping automatically, as well as one location where it didn't put a line-continuation '\' when wrapping lines on a change made to a match inside a macro definition. ===begin=== #!/bin/sh -e # Usage: # ./ldst-phys.spatch.sh > ldst-phys.spatch # spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch # patch -p1 < out.patch for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do cat <<EOF @ cpu_matches_ld_${FN} @ expression E1,E2; identifier as; @@ ld${FN}_phys(E1->as,E2) @ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @ expression E1,E2; @@ -ld${FN}_phys(E1,E2) +address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL) EOF done for FN in b w_le w_be l_le l_be q_le q_be w l q; do cat <<EOF @ cpu_matches_st_${FN} @ expression E1,E2,E3; identifier as; @@ st${FN}_phys(E1->as,E2,E3) @ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @ expression E1,E2,E3; @@ -st${FN}_phys(E1,E2,E3) +address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL) EOF done ===endit=== Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-04target-i386: remove superfluous TARGET_HAS_SMC macroEmilio G. Cota1-2/+0
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-04-02target-i386: clear bsp bit when designating bspNadav Amit1-3/+1
Since the BSP bit is writable on real hardware, during reset all the CPUs which were not chosen to be the BSP should have their BSP bit cleared. This fix is required for KVM to work correctly when it changes the BSP bit. An additional fix is required for QEMU tcg to allow software to change the BSP bit. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1427932716-11800-1-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-02target-i386: save 64-bit CR3 in 64-bit SMM state save areaPaolo Bonzini1-2/+2
The x86_64 CR3 register is 64 bits wide, save all of them! Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-03-19target-i386: Haswell-noTSX and Broadwell-noTSXEduardo Habkost1-0/+69
With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-19Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell"Eduardo Habkost1-4/+5
This reverts commit 13704e4c455770d500d6b87b117e32f0d01252c9. With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So instead of making the CPU model results confusing by making it depend on the machine-type, keep HLE and RTM on the existing Haswell and Broadwell CPU models. The plan is to introduce "Haswell-noTSX" and "Broadwell-noTSX" CPU models later, for people who have CPUs that don't have TSX feature available. Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-17target-i386: Remove icc_bridge parameter from cpu_x86_create()Eduardo Habkost2-14/+3
Instead of passing icc_bridge from the PC initialization code to cpu_x86_create(), make the PC initialization code attach the CPU to icc_bridge. The only difference here is that icc_bridge attachment will now be done after x86_cpu_parse_featurestr() is called. But this shouldn't make any difference, as property setters shouldn't depend on icc_bridge. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-17/+16
This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-03-12Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-3/+2
misc fixes and cleanups A bunch of fixes all over the place, some of the bugs fixed are actually regressions. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed Mar 11 17:48:30 2015 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (25 commits) virtio-scsi: remove empty wrapper for cmd virtio-scsi: clean out duplicate cdb field virtio-scsi: fix cdb/sense size uapi/virtio_scsi: allow overriding CDB/SENSE size virtio-scsi: drop duplicate CDB/SENSE SIZE exec: don't include hw/boards for linux-user acpi: specify format for build_append_namestring MAINTAINERS: drop aliguori@amazon.com tpm: Move memory subregion function into realize function virtio-pci: Convert to realize() pci: Convert pci_nic_init() to Error to avoid qdev_init() machine: query mem-merge machine property machine: query dump-guest-core machine property hw/boards: make it safe to include for linux-user machine: query phandle-start machine property machine: query kvm-shadow-mem machine property kvm: add machine state to kvm_arch_init machine: query kernel-irqchip property machine: allowed/required kernel-irqchip support machine: replace qemu opts with iommu property ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11machine: query kvm-shadow-mem machine propertyMarcel Apfelbaum1-2/+1
Commit e79d5a6 ("machine: remove qemu_machine_opts global list") removed the global option descriptions and moved them to MachineState's QOM properties. Query kvm-shadow-mem by accessing machine properties through designated wrappers. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2015-03-11kvm: add machine state to kvm_arch_initMarcel Apfelbaum1-1/+1
Needed to query machine's properties. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2015-03-11Merge remote-tracking branch 'remotes/afaerber/tags/qom-cpu-for-peter' into ↵Peter Maydell2-14/+3
staging QOM CPUState and X86CPU * Add CPUClass documentation * Clean up X86CPU APIC realization * Cleanups around cpu_init() # gpg: Signature made Tue Mar 10 17:27:28 2015 GMT using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" * remotes/afaerber/tags/qom-cpu-for-peter: cpu: Make cpu_init() return QOM CPUState object unicore32: Use uc32_cpu_init() m68k: Use cpu_m68k_init() target-unicore32: Make uc32_cpu_init() return UniCore32CPU target-i386: Clean up misuse of qdev_init() in realize method cpu: Add missing documentation for some CPUClass methods Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell5-222/+39
staging X86 patches queued in the last few weeks. Mostly code cleanup and changes on code assigning APIC ID. # gpg: Signature made Mon Mar 9 20:40:38 2015 GMT using RSA key ID 984DC5A6 # gpg: Can't check signature: public key not found * remotes/ehabkost/tags/x86-pull-request: target-i386: Require APIC ID to be explicitly set before CPU realize target-i386: Move APIC ID compatibility code to pc.c target-i386: Move CPUX86State::cpuid_apic_id to X86CPU::apic_id target-i386: Remove unused APIC ID default code target-i386: Eliminate unnecessary get_cpuid_vendor() function target-i386: Simplify listflags() function target-i386: Move topology.h to include/hw/i386 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
Instead of making cpu_init() return CPUArchState, return CPUState. Changes were made using the Coccinelle semantic patch below. @@ typedef CPUState; identifier e; expression args; type CPUArchState; @@ - e = + cpu = cpu_init(args); - if (!e) { + if (!cpu) { ... } - cpu = ENV_GET_CPU(env); + e = cpu->env_ptr; @@ identifier new_env, new_cpu, env, cpu; type CPUArchState; expression args; @@ -{ - CPUState *cpu = ENV_GET_CPU(env); - CPUArchState *new_env = cpu_init(args); - CPUState *new_cpu = ENV_GET_CPU(new_env); +{ + CPUState *cpu = ENV_GET_CPU(env); + CPUState *new_cpu = cpu_init(args); + CPUArchState *new_env = new_cpu->env_ptr; ... } @@ identifier c, cpu_init_func, cpu_model; type StateType, CPUType; @@ -static inline StateType* cpu_init(const char *cpu_model) -{ - CPUType *c = cpu_init_func(cpu_model); ( - if (c == NULL) { - return NULL; - } - return &c->env; | - if (c) { - return &c->env; - } - return NULL; ) -} +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model)) @@ identifier cpu_init_func; identifier model; @@ -#define cpu_init(model) (&cpu_init_func(model)->env) +#define cpu_init(model) CPU(cpu_init_func(model)) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Max Filippov <jcmvbkbc@gmail.com> [AF: Fixed up cpu_copy() manually] Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-03-10target-i386: Clean up misuse of qdev_init() in realize methodMarkus Armbruster1-6/+2
x86_cpu_apic_realize() calls qdev_init() to realize the APIC. qdev_init()'s error handling has unwanted side effects: it unparents the device, and it calls qerror_report_err(). qerror_report_err() is always inappropriate in realize methods, because it doesn't return the Error object. It either reports the error to stderr or the human monitor, or it stores it in the QMP monitor, where it makes the QMP command fail even though the realize method succeeded. Fortunately, qdev_init() can't actually fail here, because realize can't fail for any of the three possible APIC device models. Clean up by cutting out the qdev_init() middle-man: set property "realized" directly. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-03-10x86: fix SS selector in SYSRETBill Paul1-2/+2
According to my reading of the Intel documentation, the SYSRET instruction is supposed to force the RPL bits of the %ss register to 3 when returning to user mode. The actual sequence is: SS.Selector <-- (IA32_STAR[63:48]+8) OR 3; (* RPL forced to 3 *) However, the code in helper_sysret() leaves them at 0 (in other words, the "OR 3" part of the above sequence is missing). It does set the privilege level bits of %cs correctly though. This has caused me trouble with some of my VxWorks development: code that runs okay on real hardware will crash on QEMU, unless I apply the patch below. Signed-off-by: Bill Paul <wpaul@windriver.com> Message-Id: <201503091548.01462.wpaul@windriver.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-03-09target-i386: Require APIC ID to be explicitly set before CPU realizeEduardo Habkost2-1/+11
On softmuu, instead of setting APIC ID automatically when creating a X86CPU, require the property to be set before realizing the object (which is already done by the CPU creation code on PC). Keep apic_id = 0 by default on *-user so it can simply create a new CPU object and realize it without extra steps (so target-i386 will be able to use cpu_generic_init() eventually). Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-09target-i386: Move APIC ID compatibility code to pc.cEduardo Habkost2-35/+0
The APIC ID compatibility code is required only for PC, and now that x86_cpu_initfn() doesn't use x86_cpu_apic_id_from_index() anymore, that code can be moved to pc.c. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-09target-i386: Move CPUX86State::cpuid_apic_id to X86CPU::apic_idEduardo Habkost4-10/+9
The field doesn't need to be inside CPUX86State, and it is not specific for the CPUID instruction, so move and rename it. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-09target-i386: Remove unused APIC ID default codeEduardo Habkost1-1/+0
The existing apic_id = cpu_index code has no visible effect: the PC code already initializes the APIC ID according to the topology on pc_new_cpu(), and linux-user memcpy()s the CPU state (including cpuid_apic_id) on cpu_copy(). Remove the dead code and simply let APIC ID to to be 0 by default. This doesn't change behavior of PC because apic-id is already explicitly set, and doesn't affect linux-user because APIC ID was already always 0. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-09target-i386: Eliminate unnecessary get_cpuid_vendor() functionEduardo Habkost1-14/+6
The function was used in only two places. In one of them, the function made the code less readable by requiring temporary te[bcd]x variables. In the other one we can simply inline the existing code. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-09target-i386: Simplify listflags() functionEduardo Habkost1-28/+14
listflags() had lots of unnecessary complexity. Instead of printing to a buffer that will be immediately printed, simply call the printing function directly. Also, remove the fbits and flags arguments that were always set to the same value. Also, there's no need to list the flags in reverse order. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-09target-i386: Move topology.h to include/hw/i386Eduardo Habkost2-135/+1
This will allow the PC code to use the header, and lets us eliminate the QEMU_INCLUDES hack inside tests/Makefile. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-03-03Revert "Merge remote-tracking branch ↵Peter Maydell5-56/+240
'remotes/ehabkost/tags/x86-pull-request' into staging" This reverts commit b8a173b25c887a606681fc35a46702c164d5b2d0, reversing changes made to 5de090464f1ec5360c4f30faa01d8a9f8826cd58. (I applied this pull request when I should not have done so, and am now immediately reverting it.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-02Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell5-240/+56
staging * remotes/ehabkost/tags/x86-pull-request: target-i386: Move APIC ID compatibility code to pc.c target-i386: Require APIC ID to be explicitly set before CPU realize target-i386: Set APIC ID using cpu_index on CONFIG_USER linux-user: Check for cpu_init() errors target-i386: Move CPUX86State.cpuid_apic_id to X86CPU.apic_id target-i386: Simplify error handling on cpu_x86_init_user() target-i386: Eliminate cpu_init() function target-i386: Rename cpu_x86_init() to cpu_x86_init_user() target-i386: Move topology.h to include/hw/i386 target-i386: Eliminate unnecessary get_cpuid_vendor() function target-i386: Simplify listflags() function Conflicts: target-i386/cpu.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-25target-i386: Move APIC ID compatibility code to pc.cEduardo Habkost1-34/+0
The APIC ID compatibility code is required only for PC, and now that x86_cpu_initfn() doesn't use x86_cpu_apic_id_from_index() anymore, that code can be moved to pc.c. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-02-25target-i386: Require APIC ID to be explicitly set before CPU realizeEduardo Habkost2-2/+7
Instead of setting APIC ID automatically when creating a X86CPU, require the property to be set before realizing the object (which all callers of cpu_x86_create() already do). Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-02-25target-i386: Set APIC ID using cpu_index on CONFIG_USEREduardo Habkost1-0/+6
The PC CPU initialization code already sets apic-id based on the CPU topology, and CONFIG_USER doesn't need the topology-based APIC ID calculation code. Make CONFIG_USER set apic-id before realizing the CPU (just like PC already does), so we can simplify x86_cpu_initfn later. As there is no CPU topology configuration in CONFIG_USER, just use cpu_index as the APIC ID. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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