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2016-12-20Move target-* CPU file into a target/ folderThomas Huth11-5921/+0
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-11-24target-m68k: fix muluw/mulswLaurent Vivier1-1/+1
"The multiplier and multiplicand are both word operands, and the result is a long-word operand." So compute flags on a long-word result, not on a word result. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-11-24target-m68k: Fix cmpa operand sizeLaurent Vivier1-1/+1
"The size of the operation can be specified as word or long. Word length source operands are sign-extended to 32 bits for comparison." So comparison is always done using OS_LONG. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-11-24target-m68k: fix EXG instructionLaurent Vivier1-2/+2
opcodes of "EXG Ax,Ay" and "EXG Dx,Dy" have been swapped Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-11-01log: Add locking to large logging blocksRichard Henderson1-0/+2
Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: immediate ops manage word and byte operandsLaurent Vivier1-22/+35
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: cmp manages word and bytes operandsLaurent Vivier1-6/+11
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add/sub manage word and byte operandsLaurent Vivier1-33/+40
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add addressing modes to negLaurent Vivier1-8/+12
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: introduce byte and word cc_opsLaurent Vivier3-69/+93
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: some bit ops cleanupLaurent Vivier1-19/+15
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: suba/adda can manage word operandLaurent Vivier1-2/+3
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: and can manage word and byte operandsLaurent Vivier1-6/+10
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: or can manage word and byte operandsLaurent Vivier1-6/+8
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: eor can manage word and byte operandsLaurent Vivier1-6/+7
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add addressing modes to notLaurent Vivier1-4/+10
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: Inline addx, subx, negxRichard Henderson3-60/+178
Signed-off-by: Richard Henderson <rth@twiddle.net> And add opcodes for 680x0 Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-28target-m68k: add dbccLaurent Vivier1-0/+25
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add addressing modes to sccLaurent Vivier1-20/+20
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add exg opsLaurent Vivier1-0/+30
Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add linklLaurent Vivier1-5/+21
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-28target-m68k: add bkpt instructionLaurent Vivier1-0/+6
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Optimize gen_flush_flagsRichard Henderson1-4/+52
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Optimize some comparisonsRichard Henderson1-6/+103
Signed-off-by: Richard Henderson <rth@twiddle.net> [laurent: fixed VC and VS: assign v1, not v2] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Use setcond for sccRichard Henderson1-9/+11
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Introduce DisasCompareRichard Henderson1-24/+61
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Reorg flags handlingRichard Henderson7-497/+359
Separate all ccr bits. Continue to batch updates via cc_op. Signed-off-by: Richard Henderson <rth@twiddle.net> Fix gen_logic_cc() to really extend the size of the result. Fix gen_get_ccr(): update cc_op as it is used by the helper. Factorize flags computing and src/ccr cleanup Signed-off-by: Laurent Vivier <laurent@vivier.eu> target-m68k: sr/ccr cleanup Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Remove incorrect clearing of cc_xRichard Henderson1-7/+0
The CF docs certainly doesnt suggest this is true. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Some fixes to SR and flags managementRichard Henderson4-6/+21
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Print flags properlyRichard Henderson3-8/+9
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: update CPU flags managementLaurent Vivier2-40/+86
Copied from target-i386 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: don't update cc_dest in helpersLaurent Vivier4-18/+17
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: update move to/from ccr/srLaurent Vivier1-31/+22
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit()Laurent Vivier4-26/+6
Update cc_op directly from tcg_gen_insn_start() and restore_state_to_opc() Copied from target-i386 Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Replace helper_xflag_lt with setcondRichard Henderson3-13/+7
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: allow to update flags with operation on words and bytesLaurent Vivier3-84/+151
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: REG() macro cleanupLaurent Vivier1-3/+4
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: set PAGE_BITS to 12 for m68kLaurent Vivier1-2/+5
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: define operand sizesLaurent Vivier2-32/+23
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: set disassembler mode to 680x0 or coldfireLaurent Vivier1-1/+6
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: introduce read_imXX() functionsLaurent Vivier1-50/+41
Read a 8, 16 or 32bit immediat constant. An immediate constant is stored in the instruction opcode and can be in one or two extension words. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: manage scaled indexLaurent Vivier1-0/+5
Scaled index is not supported by 68000, 68008, and 68010. EA = (bd + PC) + Xn.SIZE*SCALE + od Ignore it: M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2.4 BRIEF EXTENSION WORD FORMAT COMPATIBILITY "If the MC68000 were to execute an instruction that encoded a scaling factor, the scaling factor would be ignored and would not access the desired memory address. The earlier microprocessors do not recognize the brief extension word formats implemented by newer processors. Although they can detect illegal instructions, they do not decode invalid encodings of the brief extension word formats as exceptions." Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: define m680x0 CPUs and featuresLaurent Vivier3-45/+142
This patch defines height new features: - M68K_FEATURE_SCALED_INDEX, scaled address index register - M68K_FEATURE_LONG_MULDIV, 32bit multiply/divide - M68K_FEATURE_QUAD_MULDIV, 64bit multiply/divide - M68K_FEATURE_BCCL, long conditional branches - M68K_FEATURE_BITFIELD, bit field instructions - M68K_FEATURE_FPU, FPU instructions - M68K_FEATURE_CAS, cas instruction - M68K_FEATURE_BKPT, bkpt instruction Original patch from Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-10-25target-m68k: Build the opcode table only once to avoid multithreading issuesJohn Paul Adrian Glaubitz1-0/+5
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-25target-m68k: fix DEBUG_DISPATCHLaurent Vivier1-1/+1
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-10-24exec: move cpu_exec_init() calls to realize functionsLaurent Vivier1-8/+7
Modify all CPUs to call it from XXX_cpu_realizefn() function. Remove all the cannot_destroy_with_object_finalize_yet as unsafe references have been moved to cpu_exec_realizefn(). (tested with QOM command provided by commit 4c315c27) for arm: Setting of cpu->mp_affinity is moved from arm_cpu_initfn() to arm_cpu_realizefn() as setting of cpu_index is now done in cpu_exec_realizefn(). To avoid to overwrite an user defined value, we set it to an invalid value by default, and update it in realize function only if the value is still invalid. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-10-07qemu-tech: document lazy condition code evaluation in cpu.hPaolo Bonzini1-0/+8
Unlike the other sections, they are pretty specific to a particular CPU. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-09-15Remove unused function declarationsLadi Prosek1-1/+0
Unused function declarations were found using a simple gcc plugin and manually verified by grepping the sources. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-09-13target-m68k: fix get_mac_extf helperPaolo Bonzini1-1/+1
val is assigned twice; the second one should be combined with "|". Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-07-12target-*: Clean up cpu.h header guardsMarkus Armbruster1-2/+3
Most of them use guard symbols like CPU_$target_H, but we also have __MIPS_CPU_H__ and __TRICORE_CPU_H__. They all upset scripts/clean-header-guards.pl. The script dislikes CPU_$target_H because they don't match their file name (they should, to make guard collisions less likely). The others are reserved identifiers. Clean them all up: use guard symbol $target_CPU_H for target-$target/cpu.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
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