| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2007-09-25 | Optimise instructions accessing CP0, by Aurelien Jarno. | ths | 1 | -9/+10 |
| 2007-09-24 | Per-CPU instruction decoding implementation, by Aurelien Jarno. | ths | 1 | -0/+1 |
| 2007-09-06 | Partial support for 34K multithreading, not functional yet. | ths | 1 | -41/+198 |
| 2007-06-23 | Handle MIPS64 SEGBITS value correctly. | ths | 1 | -0/+2 |
| 2007-06-03 | Move target-specific defines to the target directories. | ths | 1 | -0/+6 |
| 2007-05-31 | Don't kill the registered irqs on reset. | ths | 1 | -3/+4 |
| 2007-05-30 | Fix CPU (re-)selection on reset. | ths | 1 | -1/+4 |
| 2007-05-29 | Fix usermode check, thanks Aurelien Jarno. | ths | 1 | -1/+1 |
| 2007-05-29 | Don't check the FPU state for each FPU instruction, use hflags to | ths | 1 | -3/+5 |
| 2007-05-28 | Handle PX/UX status flags correctly, by Aurelien Jarno. | ths | 1 | -0/+1 |
| 2007-05-23 | The 24k wants more watch and srsmap registers. | ths | 1 | -2/+2 |
| 2007-05-18 | - Move FPU exception handling into helper functions, since they are big. | ths | 1 | -3/+3 |
| 2007-05-13 | MIPS linux-user update. | ths | 1 | -0/+1 |
| 2007-05-13 | MIPS TLB style selection at runtime, by Herve Poussineau. | ths | 1 | -8/+24 |
| 2007-05-07 | MIPS 64-bit FPU support, plus some collateral bugfixes in the | ths | 1 | -19/+25 |
| 2007-04-17 | Choose number of TLBs at runtime, by Herve Poussineau. | ths | 1 | -0/+1 |
| 2007-04-07 | Unify IRQ handling. | pbrook | 1 | -0/+2 |
| 2007-04-05 | 64bit MIPS FPUs have 32 registers. | ths | 1 | -2/+1 |
| 2007-03-30 | Fix typo, suggested by Ben Taylor. | ths | 1 | -1/+1 |
| 2007-03-30 | Sanitize mips exception handling. | ths | 1 | -2/+0 |
| 2007-03-23 | Fix enough FPU/R2 support to get 24Kf going. | ths | 1 | -0/+2 |
| 2007-03-18 | MIPS -cpu selection support, by Herve Poussineau. | ths | 1 | -0/+5 |
| 2007-03-02 | MIPS Userland TLS register emulation, by Daniel Jacobowitz. | ths | 1 | -0/+4 |
| 2007-02-28 | MIPS FPU dynamic activation, part 1, by Herve Poussineau. | ths | 1 | -3/+1 |
| 2007-02-20 | Replace TLSZ with TARGET_FMT_lx. | ths | 1 | -7/+0 |
| 2007-01-24 | EBase is limited to KSEG0/KSEG1 even on 64bit CPUs. | ths | 1 | -1/+1 |
| 2007-01-24 | Reworking MIPS interrupt handling, by Aurelien Jarno. | ths | 1 | -0/+1 |
| 2007-01-23 | Implementing dmfc/dmtc. | ths | 1 | -33/+34 |
| 2007-01-22 | Fix PageMask handling, second part. | ths | 1 | -2/+1 |
| 2006-12-23 | Check ELF binaries for machine type and endianness. | ths | 1 | -0/+2 |
| 2006-12-21 | Scrap SIGN_EXTEND32. | ths | 1 | -4/+1 |
| 2006-12-21 | Preliminiary MIPS64 support, disabled by default due to performance impact. | ths | 1 | -7/+22 |
| 2006-12-06 | Add MIPS32R2 instructions, and generally straighten out the instruction | ths | 1 | -4/+55 |
| 2006-12-06 | Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aid | ths | 1 | -1/+7 |
| 2006-12-06 | MIPS TLB performance improvements, by Daniel Jacobowitz. | ths | 1 | -1/+2 |
| 2006-06-14 | Solaris/SPARC host port (Ben Taylor) | bellard | 1 | -0/+7 |
| 2006-06-14 | use constants for TLB handling (Thiemo Seufer) | bellard | 1 | -1/+1 |
| 2006-06-14 | mips config fixes (initial patch by Stefan Weil) | bellard | 1 | -1/+1 |
| 2006-06-14 | MIPS FPU support (Marius Goeger) | bellard | 1 | -11/+44 |
| 2006-03-11 | Rename MIPS_HFLAG(S)_TMASK (Thiemo Seufer). | pbrook | 1 | -1/+1 |
| 2006-03-11 | e bitfields in mips TLB structures (Thiemo Seufer). | pbrook | 1 | -5/+8 |
| 2005-12-05 | MIPS fixes (Daniel Jacobowitz) | bellard | 1 | -13/+18 |
| 2005-11-20 | added CPU_COMMON and CPUState.tb_jmp_cache[] | bellard | 1 | -18/+2 |
| 2005-07-04 | correct split between helper.c and op_helper.c - cosmetics | bellard | 1 | -168/+0 |
| 2005-07-02 | MIPS target (Jocelyn Mayer) | bellard | 1 | -0/+415 |
