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path: root/target-mips/dsp_helper.c
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2013-12-09target-mips: Use macro ARRAY_SIZE where possibleStefan Weil1-18/+12
This improves readability and simplifies the code. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29target-mips: fix mipsdsp_mul_q31_q31Petar Jovanovic1-1/+1
Multiplication of two fractional word elements is not correct when sign extension/promotion is needed. This change fixes it by adding correct casts from unsigned to signed values. In addition, the tests (dpaq_sa_l_w.c and dpsq_sa_l_w.c) have been extended to trigger the current issue. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29target-mips: fix mipsdsp_trunc16_sat16_roundPetar Jovanovic1-5/+11
This change corrects rounding and saturation of Q31 fractional value in mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the corner case for PRECRQ_RS.PH, and this test case is also part of the change. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15Petar Jovanovic1-2/+2
Multiplication of Q15 fractional halfword vectors was incorrect in the previous implementation of mipsdsp_rndq15_mul_q15_q15. It failed to take element signs into account. This change fixes it, and it adds a test case for it. The change also removes unnecessary cast in the function mipsdsp_mul_q15_q15_overflowflag21(). Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-20target-mips: clean-up in BIT_INSVPetar Jovanovic1-10/+6
This is a small follow-up change to "fix incorrect behaviour for INSV". It includes two minor modifications: - sizefilter is constant so it can be moved inside of the block, - several lines of the code are replaced with a call to deposit64. No functional change. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-19target-mips: set carry bit correctly in DSPControl registerPetar Jovanovic1-3/+4
First we need to clear the bit and then we set the given value. Instruction ADDSC sets the bit and instruction ADDWC uses this bit. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-19target-mips: fix EXTPDP and setting up pos field in the DSPControl regPetar Jovanovic1-5/+5
This change makes sure that modifications of pos field in the DSPControl register do not trash other bits in the register. This bug can be triggered with the additional test case in mips32-dsp/extpdp.c in this commit. In addition to this, this change corrects incorrect calculation of the mask for EXTPDP. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-17target-mips: fix incorrect behaviour for EXTPPetar Jovanovic1-2/+1
The mask for EXTP instruction when size=31 has not been correctly calculated. The test (mips32-dsp/extp.c) has been extended to include the case that triggers the issue. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-08target-mips: fix incorrect behaviour for INSVPetar Jovanovic1-2/+2
Corner case for INSV instruction when size=32 has not been correctly implemented. The mask for size should be one bit wider, and preparing the filter variable should be aware of this case too. The test for INSV has been extended to include the case that triggers the bug. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03target-mips: fix calculation of overflow for SHLL.PH and SHLL.QBPetar Jovanovic1-24/+6
This change corrects and simplifies how discard is calculated for shift left logical vector instructions. It is used to detect overflow and set bit 22 in the DSPControl register. The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases that expose incorrectness in the previous implementation. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-15target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHRPetar Jovanovic1-13/+1
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format. Otherwise, the results are unpredictable. Once the operands were corrected in the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became visible. This change corrects the tests for MAQ_SA_W.PHL/MAQ_SA_W.PHR and fixes sign-related issue in mipsdsp_mul_q15_q15. It also removes unnecessary comment. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
2013-03-17target-mips: fix rndrashift_short_acc and code for EXTR_ instructionsPetar Jovanovic1-14/+9
Fix for rndrashift_short_acc to set correct value to higher 64 bits. This change also corrects conditions when bit 23 of the DSPControl register is set. The existing test files have been extended with several examples that trigger the issues. One bug/example in the test file for EXTR_RS_W has been found and reported by Klaus Peichl. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson1-3/+13
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-04target-mips: fix DSP overflow macro and affected routinesPetar Jovanovic1-42/+48
The previous implementation incorrectly used same macro to detect overflow for addition and subtraction. This patch makes distinction between these two, and creates separate macros. The affected routines are changed accordingly. This change also includes additions to the existing tests for SUBQ_S_PH and SUBQ_S_W that would trigger the fixed issue, and it removes dead code from the test file. The last test case in subq_s_w.c is a bug found/reported/ isolated by Klaus Peichl from Dolby. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23target-mips: fix for sign-issue in MULQ_W helperPetar Jovanovic1-1/+1
Correct sign-propagation before multiplication in MULQ_W helper. The change also fixes previously incorrect expected values in the tests for MULQ_RS.W and MULQ_S.W. Signed-off-by: Petar Jovanovic <petarj@mips.com> Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23target-mips: fix for incorrect multiplication with MULQ_S.PHPetar Jovanovic1-1/+1
The change corrects sign-related issue with MULQ_S.PH. It also includes extension to the already existing test which will trigger the issue. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno1-67/+0
DSP instruction from the (d)append sub-class can be implemented with TCG. Use a different function for these instructions are they are quite different from compare-pick sub-class. Fix BALIGN instruction for negative value, where the value should be zero-extended before being shift to the right. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: use DSP unions for reduction add instructionsAurelien Jarno1-16/+14
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: use DSP unions for unary DSP operatorsAurelien Jarno1-82/+42
This allow to reduce the number of macros. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: use DSP unions for binary DSP operatorsAurelien Jarno1-268/+116
This allow to reduce the number of macros. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31target-mips: add unions to access DSP elementsAurelien Jarno1-0/+22
Instead of playing with bit shifting, add two unions (one for 32-bit values, one for 64-bit ones) to access all the DSP elements with the correct type. This make the code easier to read and less error prone, and allow GCC to vectorize the code in some cases. Reviewed-by: Eric Johnson <ericj@mips.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-08target-mips: Fix helper and tests for dot/cross-dot product instructionsPetar Jovanovic1-1/+1
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectly defines halfword vector elements as unsigned values. This results in wrong output which is not triggered in the tests as they also follow this logic. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01Fix my email addressDongxue Zhang1-1/+1
Fix my email address, last time it's wrong. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01target-mips: Fix for helpers for EXTR_* instructionsPetar Jovanovic1-35/+10
The change removes some unnecessary and incorrect code for EXTR_S.H. Further, it corrects the mask for shift value in the EXTR_ instructions. It also extends the existing tests so they trigger the issues corrected with the change. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01target-mips: Fix incorrect reads and writes to DSPControl registerPetar Jovanovic1-0/+8
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32 these bits must be written as zero, and return zero on read. The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes the tests that use these instructions, and makes them smaller and simpler. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-06target-mips: Fix incorrect shift for SHILO and SHILOVPetar Jovanovic1-8/+9
helper_shilo has not been shifting an accumulator value correctly for negative values in 'shift' field. Minor optimization for shift=0 case. This change also adds tests that will trigger issue and check for regressions. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-06target-mips: Fix incorrect code and test for INSVPetar Jovanovic1-1/+1
Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-11-05target-mips: use ULL for 64 bit constantsBlue Swirl1-2/+2
Fix build on a 32 bit host: CC mips-softmmu/target-mips/dsp_helper.o /src/qemu/target-mips/dsp_helper.c: In function 'helper_dextr_rs_w': /src/qemu/target-mips/dsp_helper.c:3556: error: integer constant is too large for 'long' type /src/qemu/target-mips/dsp_helper.c: In function 'helper_extr_s_h': /src/qemu/target-mips/dsp_helper.c:3656: error: integer constant is too large for 'long' type Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu1-0/+609
Add MIPS ASE DSP Accumulator and DSPControl Access instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu1-0/+233
Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu1-0/+55
Add MIPS ASE DSP Bit/Manipulation instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu1-0/+923
Add MIPS ASE DSP Multiply instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu1-0/+256
Add MIPS ASE DSP GPR-Based Shift instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu1-0/+894
Add MIPS ASE DSP Arithmetic instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP internal functionsJia Liu1-0/+1063
Add internal functions using by MIPS ASE DSP instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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