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path: root/target-mips/helper.c
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2007-10-29Fix logic bug which broke TLBL/TLBS handling somewhat.ths1-3/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3478 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28Implement missing MIPS supervisor mode bits.ths1-3/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-4/+4
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-13Fix off-by-one in address check.ths1-11/+8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3382 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths1-8/+8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-29Supervisor mode implementation, by Aurelien Jarno.ths1-27/+34
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3267 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-26hflags computation cleanup, by Aurelien Jarno.ths1-7/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3243 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths1-0/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3235 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-6/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in ↵ths1-1/+1
the regex. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths1-3/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-27/+30
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths1-3/+6
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-25MIPS64 improvements, based on a patch by Aurelien Jarno.ths1-3/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3021 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-13/+12
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3011 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-0/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2892 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-23The 24k wants more watch and srsmap registers.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths1-5/+46
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2820 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13MMU code improvements, by Aurelien Jarno.ths1-12/+10
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2811 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-31/+41
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-09Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno.ths1-5/+57
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2794 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-0/+3
conditional branch handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07Clear BD slot on next exception if appropriate.ths1-0/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2777 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-13Another fix for CP0 Cause register handling.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2658 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07cpu_get_phys_page_debug should return target_phys_addr_tj_mayer1-2/+2
instead of target_ulong to be consistent. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2633 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-06Fix handling of ADES exceptions.ths1-1/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2623 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05fix branch delay slot cornercases.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2615 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05Handle EBase properly.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2613 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30Squash logic bugs while they are fresh...ths1-1/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2547 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30Sanitize mips exception handling.ths1-25/+20
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2546 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-18Fix BD flag handling, cause register contents, implement some more bitsths1-3/+11
for R2 interrupt handling. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths1-6/+6
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2444 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-18Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2433 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-22Fix PageMask handling, second part.ths1-14/+33
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2345 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-21Bring TLB / PageSize handling in line with real hardware behaviour.ths1-17/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2341 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-03moved invalidate_tlb() to helper.c as a work around for gcc 3.2.2 bug - ↵bellard1-0/+41
suppressed invalid tb_invalidate_page_range() calls git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2287 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21Scrap SIGN_EXTEND32.ths1-10/+10
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2251 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths1-17/+17
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-10Handle invalid accesses as SIGILL for mips/mipsel userland emulation.ths1-0/+7
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2235 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-07Fix reset handling, CP0 isn't enabled by default (a fact which doesn'tths1-35/+20
matter when running in kernel space). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2228 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06Add MIPS32R2 instructions, and generally straighten out the instructionths1-6/+0
decoding. This is also the first percent towards MIPS64 support. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06MIPS TLB performance improvements, by Daniel Jacobowitz.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2220 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-26consistent update of ERL and EXLbellard1-1/+3
(Dirk Behme) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2028 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-14use constants for TLB handling (Thiemo Seufer)bellard1-32/+35
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1978 c046a42c-6fe2-441c-8c8c-71466251a162
2006-05-22fix wrong bitmasks for CP0_Context and CP0_EntryHi (Thiemo Seufer)bellard1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1937 c046a42c-6fe2-441c-8c8c-71466251a162
2006-05-22cosmetics (Thiemo Seufer)bellard1-4/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1936 c046a42c-6fe2-441c-8c8c-71466251a162
2006-05-22mips cleanup (Thiemo Seufer)bellard1-2/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1934 c046a42c-6fe2-441c-8c8c-71466251a162
2006-03-11Clear MIPS_HFLAG_BMASK for ErrorEPC (Thiemo Seufer).pbrook1-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1777 c046a42c-6fe2-441c-8c8c-71466251a162
2006-03-11e bitfields in mips TLB structures (Thiemo Seufer).pbrook1-6/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1774 c046a42c-6fe2-441c-8c8c-71466251a162
2005-12-05MIPS fixes (Daniel Jacobowitz)bellard1-7/+14
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1690 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-03 16:09:30 +0000