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path: root/target-mips/op.c
AgeCommit message (Expand)AuthorFilesLines
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths1-37/+9
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-0/+18
2007-05-28MIPS64 addressing fixes, by Aurelien Jarno.ths1-0/+16
2007-05-23The 24k wants more watch and srsmap registers.ths1-11/+11
2007-05-23The previous patch to make breakpoints work was a performanceths1-10/+0
2007-05-20Fix indexed FP load/store instructions.ths1-0/+1
2007-05-19More MIPS 64-bit FPU support.ths1-20/+48
2007-05-19Fix slti/sltiu for MIPS64, by Aurelien Jarno.ths1-6/+6
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths1-534/+105
2007-05-18Work around the lack of proper handling for self-modifying code.ths1-0/+10
2007-05-16More generic 64 bit multiplication support, by Aurelien Jarno.ths1-2/+2
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths1-2/+4
2007-05-13Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths1-63/+15
2007-05-13Delete misleading comment.ths1-2/+0
2007-05-13MMU code improvements, by Aurelien Jarno.ths1-1/+1
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-12/+5
2007-05-11Implemented cabs FP instructions, and improve exception handling forths1-0/+97
2007-05-11Implement FP madd/msub, wire up bc1any[24][ft].ths1-0/+55
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths1-0/+16
2007-05-08Work around gcc's mips define, spotted by Stefan Weil.ths1-12/+12
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-202/+718
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-2/+2
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths1-2/+2
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths1-12/+11
2007-04-14Restart interrupts after an exception.ths1-1/+14
2007-04-13Another fix for CP0 Cause register handling.ths1-1/+1
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths1-9/+5
2007-04-09Fix CP0_IntCtl handling.ths1-2/+3
2007-04-09Proper handling of reserved bits in the context register.ths1-1/+1
2007-04-09Mark watchpoint features as unimplemented.ths1-3/+8
2007-04-09Fix exception handling cornercase for rdhwr.ths1-26/+4
2007-04-07Fix ins/ext cornercase.ths1-4/+4
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths1-5/+17
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths1-11/+8
2007-04-05Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths1-19/+49
2007-04-01Actually enable 64bit configuration.ths1-5/+5
2007-03-30Sanitize mips exception handling.ths1-24/+27
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths1-1/+13
2007-03-18Fix BD flag handling, cause register contents, implement some more bitsths1-1/+6
2007-03-02MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths1-0/+7
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths1-9/+0
2007-02-27Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths1-1/+1
2007-02-18Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths1-1/+1
2007-01-24EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths1-17/+2
2007-01-24Reworking MIPS interrupt handling, by Aurelien Jarno.ths1-51/+11
2007-01-23Implementing dmfc/dmtc.ths1-45/+191
2007-01-01Fix bad data type.ths1-1/+1
2006-12-21Scrap SIGN_EXTEND32.ths1-51/+51
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths1-89/+407
2006-12-07Fix build of MIPS target without FPU support.ths1-0/+2
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