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path: root/target-mips/op.c
AgeCommit message (Expand)AuthorFilesLines
2007-11-17Fix int/float inconsistencies.pbrook1-4/+4
2007-11-09Use FORCE_RET, scrap RETURN which was implemented in target-specific code.ths1-371/+371
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths1-12/+12
2007-10-29Restrict CP0_PerfCnt to legal values.ths1-1/+1
2007-10-28Implement missing MIPS supervisor mode bits.ths1-3/+7
2007-10-27Add sharable clz/clo inline functions and use them for the mips target.ths1-49/+18
2007-10-26The other half of the mul64 rework. Sorry for the breakage, I committedths1-2/+2
2007-10-24Force proper sign extension for mfc0/mfhc0 on MIPS64.ths1-2/+2
2007-10-23Fix writable length of the index register.ths1-1/+8
2007-10-23Fix CLO calculation for MIPS64. And a small code cleanup.ths1-5/+5
2007-10-09Use always_inline in the MIPS support where applicable.ths1-2/+2
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths1-12/+12
2007-09-26hflags computation cleanup, by Aurelien Jarno.ths1-54/+4
2007-09-25Timer start/stop implementation, by Aurelien Jarno.ths1-3/+10
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths1-21/+20
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-10/+7
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths1-1/+1
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-90/+785
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths1-6/+9
2007-06-25MIPS64 improvements, based on a patch by Aurelien Jarno.ths1-2/+2
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-2/+3
2007-06-22Fix write to K0 bits in Config0, by Aurelien Jarno.ths1-1/+1
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths1-37/+9
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-0/+18
2007-05-28MIPS64 addressing fixes, by Aurelien Jarno.ths1-0/+16
2007-05-23The 24k wants more watch and srsmap registers.ths1-11/+11
2007-05-23The previous patch to make breakpoints work was a performanceths1-10/+0
2007-05-20Fix indexed FP load/store instructions.ths1-0/+1
2007-05-19More MIPS 64-bit FPU support.ths1-20/+48
2007-05-19Fix slti/sltiu for MIPS64, by Aurelien Jarno.ths1-6/+6
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths1-534/+105
2007-05-18Work around the lack of proper handling for self-modifying code.ths1-0/+10
2007-05-16More generic 64 bit multiplication support, by Aurelien Jarno.ths1-2/+2
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths1-2/+4
2007-05-13Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths1-63/+15
2007-05-13Delete misleading comment.ths1-2/+0
2007-05-13MMU code improvements, by Aurelien Jarno.ths1-1/+1
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-12/+5
2007-05-11Implemented cabs FP instructions, and improve exception handling forths1-0/+97
2007-05-11Implement FP madd/msub, wire up bc1any[24][ft].ths1-0/+55
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths1-0/+16
2007-05-08Work around gcc's mips define, spotted by Stefan Weil.ths1-12/+12
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-202/+718
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-2/+2
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths1-2/+2
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths1-12/+11
2007-04-14Restart interrupts after an exception.ths1-1/+14
2007-04-13Another fix for CP0 Cause register handling.ths1-1/+1
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths1-9/+5
2007-04-09Fix CP0_IntCtl handling.ths1-2/+3
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