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path: root/target-mips/op_helper.c
AgeCommit message (Expand)AuthorFilesLines
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths1-8/+8
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-292/+313
2007-06-28Simplify round/ceil/floor implementation, spotted by Fabrice Bellard.ths1-30/+12
2007-06-27Fix computation for ceil, floor and round instructions.ths1-6/+24
2007-06-26Implement recip1/recip2/rsqrt1/rsqrt2.ths1-90/+140
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-1/+1
2007-06-03Clean up of some target specifics in exec.c/cpu-exec.c.ths1-4/+0
2007-05-31Add proper float*_is_nan prototypes.ths1-1/+0
2007-05-28Fix ddivu for 32bit hosts, by Aurelien Jarno.ths1-4/+4
2007-05-20Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.ths1-2/+23
2007-05-19More MIPS 64-bit FPU support.ths1-0/+92
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths1-0/+541
2007-05-16More generic 64 bit multiplication support, by Aurelien Jarno.ths1-14/+0
2007-05-13Full MIPS64 MMU implementation, by Aurelien Jarno.ths1-0/+3
2007-05-13MMU code improvements, by Aurelien Jarno.ths1-5/+13
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-43/+21
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-11/+9
2007-04-15Fix qemu SIGFPE caused by division-by-zero due to underflow.ths1-0/+11
2007-04-15Delete unused define.ths1-2/+0
2007-04-13Nicer Log formatting.ths1-1/+1
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths1-11/+27
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths1-4/+2
2007-04-02Build fix for 64bit machines. (This is still not correct mul/div handling.)ths1-6/+12
2007-04-01Actually enable 64bit configuration.ths1-3/+3
2007-04-01MIPS64 configurations.ths1-2/+0
2007-03-30Sanitize mips exception handling.ths1-3/+5
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths1-2/+7
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths1-2/+0
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths1-3/+3
2007-02-18Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths1-1/+1
2007-01-24Reworking MIPS interrupt handling, by Aurelien Jarno.ths1-0/+5
2007-01-23Implementing dmfc/dmtc.ths1-6/+6
2007-01-22Fix PageMask handling, second part.ths1-0/+2
2007-01-21Bring TLB / PageSize handling in line with real hardware behaviour.ths1-8/+0
2007-01-03moved invalidate_tlb() to helper.c as a work around for gcc 3.2.2 bug - suppr...bellard1-45/+3
2007-01-01Simplify code and fix formatting.ths1-6/+6
2006-12-21Scrap SIGN_EXTEND32.ths1-6/+6
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths1-16/+130
2006-12-06Add MIPS32R2 instructions, and generally straighten out the instructionths1-3/+3
2006-12-06Dynamically translate MIPS mtc0 instructions.ths1-216/+31
2006-12-06Dynamically translate MIPS mfc0 instructions.ths1-143/+15
2006-12-06MIPS TLB performance improvements, by Daniel Jacobowitz.ths1-6/+48
2006-11-12Avoid redundant TLB flushes (Daniel Jacobowitz).pbrook1-0/+9
2006-06-26consistent update of ERL and EXLbellard1-4/+0
2006-06-14MIPS FPU support (Marius Goeger)bellard1-0/+41
2006-05-22fix wrong bitmasks for CP0_Context and CP0_EntryHi (Thiemo Seufer)bellard1-2/+2
2006-05-22cosmetics (Thiemo Seufer)bellard1-10/+7
2006-04-23removed unnecessary headerbellard1-1/+0
2006-03-11Avoid flushing of global TLB entries for differing ASIDs (Thiemo Seufer).pbrook1-2/+3
2006-03-11e bitfields in mips TLB structures (Thiemo Seufer).pbrook1-30/+22