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path: root/target-mips/translate.c
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2016-03-30target-mips: add MAAR, MAARI registerYongbok Kim1-0/+52
2016-03-30target-mips: use CP0_CHECK for gen_m{f|t}hc0Yongbok Kim1-25/+21
2016-03-30target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae1-10/+52
2016-03-30target-mips: check CP0 enabled for CACHE instruction also in R6Leon Alrae1-0/+1
2016-03-30hw/mips_malta: add CPS to Malta boardLeon Alrae1-0/+10
2016-03-30target-mips: add CMGCRBase registerYongbok Kim1-0/+18
2016-03-23target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUsLeon Alrae1-0/+1
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova1-1/+1
2016-02-26target-mips: implement R6 multi-threadingYongbok Kim1-0/+59
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-12/+13
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-01-23mips: Clean up includesPeter Maydell1-0/+1
2016-01-23target-mips: Fix ALIGN instruction when bp=0Miodrag Dinic1-1/+10
2015-10-30target-mips: add SIGRIE instructionYongbok Kim1-1/+11
2015-10-30target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim1-3/+25
2015-10-29target-mips: Add enum for BREAK32Yongbok Kim1-1/+2
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-2/+4
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-43/+5
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-4/+5
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+6
2015-10-07target-mips: Add delayed branch state to insn_startRichard Henderson1-1/+2
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-15/+10
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-3/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-5/+4
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-18target-mips: improve exception handlingPavel Dovgaluk1-191/+174
2015-09-18target-mips: correct MTC0 instruction on MIPS64Leon Alrae1-11/+7
2015-09-18target-mips: add missing restriction in DAUI instructionLeon Alrae1-1/+3
2015-09-18target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONSAurelien Jarno1-39/+0
2015-09-18target-mips: get rid of MIPS_DEBUGAurelien Jarno1-605/+19
2015-09-18target-mips: remove wrong checks for recip.fmt and rsqrt.fmtPetar Jovanovic1-4/+2
2015-09-18target-mips: Use tcg_gen_extrh_i64_i32Richard Henderson1-26/+22
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-2/+2
2015-08-13target-mips: simplify LWL/LDL mask generationAurelien Jarno1-8/+6
2015-08-04target-mips: Copy restrictions from ext/ins to dext/dinsRichard Henderson1-20/+25
2015-08-04target-mips: fix semihosting for microMIPS R6Leon Alrae1-3/+7
2015-07-15target-mips: fix page fault address for LWL/LWR/LDL/LDRAurelien Jarno1-0/+12
2015-07-15target-mips: fix logically dead code reported by CoverityLeon Alrae1-0/+3
2015-06-26target-mips: microMIPS32 R6 POOL16{A, C} instructionsYongbok Kim1-15/+118
2015-06-26target-mips: microMIPS32 R6 Major instructionsYongbok Kim1-17/+45
2015-06-26target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim1-6/+21
2015-06-26target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim1-32/+199
2015-06-26target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim1-10/+72
2015-06-26target-mips: microMIPS32 R6 branches and jumpsYongbok Kim1-40/+202
2015-06-26target-mips: add microMIPS32 R6 opcode enumYongbok Kim1-16/+103
2015-06-26target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim1-0/+68
2015-06-26target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim1-33/+45
2015-06-26target-mips: rearrange gen_compute_compact_branchYongbok Kim1-236/+236
2015-06-26target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAPYongbok Kim1-67/+99
2015-06-26target-mips: remove an unused argumentYongbok Kim1-3/+2
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