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peter/qemu
bdrv-getlength-conversion
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block-dmg
block-dmg-2.2
block-dmg-2.3
block-dmg-2.3-v2
doc-updates
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gtk-toggle-menubar
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QEMU hacking for Peter
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target-mips
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translate.c
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Commit message (
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Author
Files
Lines
2012-10-31
target-mips: correctly restore btarget upon exception
Aurelien Jarno
1
-0
/
+11
2012-10-31
target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
Aurelien Jarno
1
-36
/
+0
2012-10-31
target-mips: Add ASE DSP accumulator instructions
Jia Liu
1
-0
/
+351
2012-10-31
target-mips: Add ASE DSP compare-pick instructions
Jia Liu
1
-0
/
+350
2012-10-31
target-mips: Add ASE DSP bit/manipulation instructions
Jia Liu
1
-0
/
+249
2012-10-31
target-mips: Add ASE DSP multiply instructions
Jia Liu
1
-0
/
+485
2012-10-31
target-mips: Add ASE DSP GPR-based shift instructions
Jia Liu
1
-0
/
+324
2012-10-31
target-mips: Add ASE DSP arithmetic instructions
Jia Liu
1
-3
/
+792
2012-10-31
target-mips: Add ASE DSP load instructions
Jia Liu
1
-0
/
+88
2012-10-31
target-mips: Add ASE DSP branch instructions
Jia Liu
1
-0
/
+36
2012-10-31
Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
Jia Liu
1
-27
/
+95
2012-10-31
target-mips: Add ASE DSP resources access check
Jia Liu
1
-0
/
+23
2012-10-28
target-mips: Use TCG registers for the FPU.
Richard Henderson
1
-42
/
+54
2012-09-27
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
Richard Henderson
1
-1
/
+2
2012-09-19
target-mips: Implement Loongson Multimedia Instructions
Richard Henderson
1
-3
/
+376
2012-09-19
target-mips: Always evaluate debugging macro arguments
Richard Henderson
1
-14
/
+17
2012-09-19
target-mips: Fix MIPS_DEBUG.
Richard Henderson
1
-36
/
+38
2012-09-19
target-mips: Set opn in gen_ldst_multiple.
Richard Henderson
1
-0
/
+6
2012-09-15
target-mips: switch to AREG0 free mode
Blue Swirl
1
-368
/
+386
2012-09-08
MIPS/user: Fix reset CPU state initialization
Maciej W. Rozycki
1
-13
/
+3
2012-08-27
target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
Eric Johnson
1
-1
/
+9
2012-08-27
target-mips: add privilege level check to several Cop0 instructions
Eric Johnson
1
-0
/
+9
2012-08-27
mips-linux-user: Always support rdhwr.
Richard Henderson
1
-0
/
+4
2012-08-27
target-mips: Streamline indexed cp1 memory addressing.
Richard Henderson
1
-2
/
+1
2012-08-27
Fix order of CVT.PS.S operands
Richard Sandiford
1
-1
/
+1
2012-08-27
Fix operands of RECIP2.S and RECIP2.PS
Richard Sandiford
1
-2
/
+2
2012-08-23
target-mips: Enable access to required RDHWR hardware registers
Meador Inge
1
-2
/
+3
2012-08-09
MIPS: Correct FCR0 initialization
Nathan Froyd
1
-0
/
+1
2012-06-04
target-mips: Let cpu_mips_init() return MIPSCPU
Andreas Färber
1
-2
/
+2
2012-06-04
target-mips: Use cpu_reset() in cpu_mips_init()
Andreas Färber
1
-1
/
+1
2012-05-19
mips: Fix BC1ANY[24]F instructions
Richard Sandiford
1
-4
/
+4
2012-04-30
target-mips: Start QOM'ifying CPU init
Andreas Färber
1
-1
/
+0
2012-04-30
target-mips: QOM'ify CPU
Andreas Färber
1
-1
/
+3
2012-03-14
target-mips: Don't overuse CPUState
Andreas Färber
1
-178
/
+178
2012-03-14
Rename cpu_reset() to cpu_state_reset()
Andreas Färber
1
-2
/
+2
2012-02-28
target-mips: Clean includes
Stefan Weil
1
-7
/
+0
2011-09-06
mips: Initialize MT state at reset
Edgar E. Iglesias
1
-0
/
+26
2011-09-06
mips: Hook in more reg accesses via mttr/mftr
Edgar E. Iglesias
1
-0
/
+86
2011-08-20
Use glib memory allocation and free functions
Anthony Liguori
1
-1
/
+1
2011-06-26
Remove exec-all.h include directives
Blue Swirl
1
-1
/
+0
2011-04-20
Remove unused function parameters from gen_pc_load and rename the function
Stefan Weil
1
-2
/
+1
2011-04-10
Fix conversions from pointer to tcg_target_long
Stefan Weil
1
-1
/
+1
2011-01-24
target-mips: fix save_cpu_state() calls
Aurelien Jarno
1
-6
/
+6
2011-01-18
mips: Break TBs after mfc0_count
Edgar E. Iglesias
1
-2
/
+6
2010-12-22
target-mips: fix translation of MT instructions
Nathan Froyd
1
-4
/
+4
2010-10-30
target-xxx: Use fprintf_function (format checking)
Stefan Weil
1
-7
/
+5
2010-10-13
mips: avoid write only variables
Blue Swirl
1
-0
/
+29
2010-07-31
Correctly identify multiple cpus in SMP systems
Hervé Poussineau
1
-2
/
+1
2010-07-25
mips: more fixes to the MIPS interrupt glue logic
Aurelien Jarno
1
-2
/
+10
2010-07-11
target-mips: add loongson 2E & 2F integer instructions
Aurelien Jarno
1
-0
/
+271
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