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path: root/target-mips/translate.c
AgeCommit message (Expand)AuthorFilesLines
2007-06-02Check for R2 instructions, and throw RI if we don't emulate R2.ths1-18/+50
2007-06-01Make sure hflags are updated for CP0_Status changes.ths1-8/+42
2007-05-31Simplify code.ths1-4/+4
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths1-84/+110
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-7/+26
2007-05-28MIPS64 addressing fixes, by Aurelien Jarno.ths1-9/+49
2007-05-23The 24k wants more watch and srsmap registers.ths1-247/+31
2007-05-23The previous patch to make breakpoints work was a performanceths1-22/+7
2007-05-20Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.ths1-8/+8
2007-05-20Fix indexed FP load/store instructions.ths1-17/+28
2007-05-19More MIPS 64-bit FPU support.ths1-37/+179
2007-05-19Fix slti/sltiu for MIPS64, by Aurelien Jarno.ths1-2/+2
2007-05-19Fix ldl/ldr implementation, by Aurelien Jarno.ths1-0/+2
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths1-101/+75
2007-05-18Work around the lack of proper handling for self-modifying code.ths1-2/+20
2007-05-13Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.ths1-57/+57
2007-05-13Don't decode CP0 XContext on 32bit MIPS.ths1-4/+8
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-9/+16
2007-05-11Implemented cabs FP instructions, and improve exception handling forths1-40/+83
2007-05-11Another bit of nicer debug output.ths1-1/+1
2007-05-11Implement FP madd/msub, wire up bc1any[24][ft].ths1-12/+85
2007-05-11Improved debug output for the MIPS opcode decoder.ths1-85/+77
2007-05-10Fix for the scd instruction, by Aurelien Jarno.ths1-0/+1
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths1-2/+2
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-243/+824
2007-04-25Next attempt to get the lui sign extension right.ths1-2/+1
2007-04-25Fix lui sign extension.ths1-1/+1
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-4/+0
2007-04-16Simplify branch likely handling.ths1-6/+8
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths1-4/+4
2007-04-15Small code generation optimization.ths1-3/+6
2007-04-14Restart interrupts after an exception.ths1-8/+19
2007-04-11Make SYNCI_Step and CCRes CPU-specific.ths1-3/+0
2007-04-11Throw RI for invalid MFMC0-class instructions. Introduce optionalths1-3/+13
2007-04-11Code formatting fix.ths1-935/+938
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths1-1/+5
2007-04-09Fix CP0_IntCtl handling.ths1-0/+3
2007-04-09Mark watchpoint features as unimplemented.ths1-0/+1
2007-04-09Catch unaligned sc/scd.ths1-0/+2
2007-04-09Fix exception handling cornercase for rdhwr.ths1-11/+5
2007-04-09Remove bogus mtc0 handling.ths1-10/+0
2007-04-07Implement prefx.ths1-1/+41
2007-04-07Set proper BadVAddress value for unaligned instruction fetch.ths1-1/+2
2007-04-07Actually skip over delay slot for a non-taken branch likely.ths1-2/+2
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths1-0/+1
2007-04-05fix branch delay slot cornercases.ths1-2/+5
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths1-33/+93
2007-04-05Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths1-73/+82
2007-04-04Fix code formatting.ths1-66/+66
2007-04-02MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths1-2/+9
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