summaryrefslogtreecommitdiff
path: root/target-mips/translate_init.c
AgeCommit message (Collapse)AuthorFilesLines
2014-12-16target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki1-19/+21
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki1-1/+1
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki1-0/+41
Add the M14K and M14Kc processors from MIPS Technologies that are the original implementation of the microMIPS ISA. They are dual instruction set processors, implementing both the microMIPS and the standard MIPSr32 ISA. These processors correspond to the M4K and 4KEc CPUs respectively, except with support for the microMIPS instruction set added, support for the MCU ASE added and two extra interrupt lines, making a total of 8 hardware interrupts plus 2 software interrupts. The remaining parts of the microarchitecture, in particular the pipeline, stayed unchanged. The presence of the microMIPS ASE is is reflected in the configuration added. We currently have no support for the MCU ASE, including in particular the ACLR, ASET and IRET instructions in either encoding, and we have no support for the extra interrupt lines, including bits in CP0.Status and CP0.Cause registers, so these features are not marked, making our support diverge from real hardware. Signed-off-by: Sandra Loosemore <sandra@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Add 5KEc and 5KEf MIPS64r2 processorsMaciej W. Rozycki1-0/+45
Add the 5KEc and 5KEf processors from MIPS Technologies that are the original implementation of the MIPS64r2 ISA. Silicon for these processors has never been taped out and no soft cores were released even. They do exist though, a CP0.PRId value has been assigned and experimental RTLs produced at the time the MIPS64r2 ISA has been finalized. The settings introduced here faithfully reproduce that hardware. As far the implementation goes these processors are the same as the 5Kc and the 5Kf CPUs respectively, except implementing the MIPS64r2 rather than the original MIPS64 instruction set. There must have been some updates to the CP0 architecture as mandated by the ISA, such as the addition of the EBase register, although I am not sure about the exact details, no documentation has ever been produced for these processors. The remaining parts of the microarchitecture, in particular the pipeline, stayed unchanged. Or to put it another way, the difference between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE CPU, except for the 64-bit rather than 32-bit ISA. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-07mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bitsMaciej W. Rozycki1-3/+5
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit and the CP0.Config3.DSP bit for the artificial mips32r5-generic and mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags' and CPUs that implement that ASE need to have both CP0.Config3.DSP and CP0.Config3.DSP2P set or software won't detect its presence. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove DSP flags from mips32r5-generic] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA support to mips32r5-genericYongbok Kim1-2/+2
add MSA support to mips32r5-generic core definition Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim1-0/+34
add msa_reset() and global msa register (d type only) Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: enable features in MIPS64R6-generic CPULeon Alrae1-2/+9
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add TLBINV supportLeon Alrae1-0/+2
For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-0/+2
PageGrain needs rw bitmask which differs between MIPS architectures. In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable, whereas in R6 they are read-only 1. On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward compatiblity, therefore there are separate mtc0 and dmtc0 helpers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-14target-mips: define a new generic CPU supporting MIPS64 Release 6 ISALeon Alrae1-0/+30
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell1-11/+11
Add U suffix to various places where we shift a 1 left by 31, to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-1/+3
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-10target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic1-4/+5
Description of UFR feature: Required in MIPS32r5 if floating point is implemented and user-mode FR switching is supported. The UFR register allows user-mode to clear StatusFR by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by executing a CFC1 to UFR. helper_ctc1 has been extended with an additional parameter rt to check requirements for UFR feature. Definition of mips32r5-generic has been modified to include support for UFR. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic1-1/+11
Add CP0_Config5, define rw_bitmask and enable modifications. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic1-1/+8
Add CP0_Config4, define rw_bitmask. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2014-02-10target-mips: add CPU definition for MIPS32R5Petar Jovanovic1-0/+25
Add mips32r5-generic among CPU definitions for MIPS. Define ISA_MIPS32R3 and ISA_MIPS32R5. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2013-08-03target-mips: fix 34Kf configuration for DSP ASEYongbok Kim1-4/+3
34Kf core does support DSP ASE. CP0_Config3 configuration for 34Kf and description are wrong. Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP processorsJia Liu1-0/+52
Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-09-06mips: Default to using one VPE and one TC.Edgar E. Iglesias1-1/+1
Boards can override the setup if needed. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Enable VInt interrupt mode for the 34KfEdgar E. Iglesias1-1/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-2/+2
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-05-08Fix typos in comments (interupt -> interrupt)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-06Fix typo in code and commentsStefan Weil1-1/+1
Replace writeable -> writable Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-1/+1
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-31Remove unused constantHervé Poussineau1-4/+0
Remove unused constant MIPS_FCR0 Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29MIPS: Initial support of fulong mini pc (CPU definition)Huacai Chen1-0/+35
Signed-off-by: Huacai Chen <zltjiangshi@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-17target-mips: No MIPS16 support for 4Kc, 4KEc coresStefan Weil1-3/+3
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487. 4Kc and 4KEc don't support MIPS16. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-16target-mips: 4Kc, 4KEc cores do not support MIPS16Stefan Weil1-3/+3
4Kc, 4KEc cores do not support MIPS16, so not only the CP0_Config1 had to be fixed (see previous patch), but also MIPS16 instructions must not be executed. (Hint from Nathan Froyd, thanks). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: fix user-mode emulation startupNathan Froyd1-8/+0
Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: set Config1.CA for MIPS16-aware CPUsNathan Froyd1-9/+18
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno1-0/+32
Depending on the CPU, CP0_LLAddr is either read-only or read-write, and the returned value can be shifted by a variable amount of bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-14mips: fix cpu_reset memory leakBlue Swirl1-50/+0
Remove cpu_mips_register() - move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init() - move the other parts in cpu_mips_init() Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-10/+10
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-10/+10
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-03-08target-mips: rename helpers from do_ to helper_aurel321-4/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14target-mips: fix indentationaurel321-42/+42
Remove all tabs from target-mips/* Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6306 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12target-mips: get rid of tests on env->user_mode_onlyaurel321-10/+10
Replace runtime checks on env->user_mode_only by compile time checks on CONFIG_USER_ONLY. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6276 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-2/+2
Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18Move the active FPU registers into env again, and use more TCG registersths1-3/+6
to access them. Signed-off-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14target-mips: fix warningaurel321-1/+1
Attached patch fixes a warning in cpu_mips_find_by_name(). 'name' is a string, so it should be declared as char*, not unsigned char*. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5213 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02Build fix for gcc-3.3.ths1-0/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5139 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23Less hardcoding of TARGET_USER_ONLY.ths1-15/+12
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-21A bunch of minor code improvements in the MIPS target.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4921 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-20Fix compiler warning, by Stefan Weil.ths1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4915 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-27More efficient target register / TC accesses.ths1-2/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4794 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.ths1-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4604 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06Enable 64-bit FPU only for NewABI. Spotted by Vince Weaver.ths1-0/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4368 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-12 13:08:56 +0000