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path: root/target-mips/translate_init.c
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2007-12-28Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.ths1-3/+3
2007-12-25Support for VR5432, and some of its special instructions. Original patchths1-0/+16
2007-12-255K and 20K are Release 1 CPUs.ths1-3/+3
2007-12-25Improved PABITS handling, and config register fixes.ths1-50/+99
2007-12-24Fix CCRes value for 20Kc.ths1-1/+1
2007-11-19Add older 4Km variants.ths1-0/+34
2007-11-18Use a valid PRid.ths1-1/+1
2007-11-14Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths1-2/+19
2007-11-10added cpu_model parameter to cpu_init()bellard1-22/+11
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths1-2/+2
2007-10-29Preliminary MIPS64R2 mode.ths1-0/+21
2007-10-23Use the standard ASE check for MIPS-3D and MT.ths1-1/+1
2007-09-30Code provision for n32/n64 mips userland emulation. Not functional yet.ths1-2/+2
2007-09-29Supervisor mode implementation, by Aurelien Jarno.ths1-3/+3
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-1/+13
2007-09-23Fix mips usermode emulation.ths1-0/+3
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-53/+158
2007-08-26Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths1-7/+9
2007-07-29Fix MIPS cache configuration, by Aurelien Jarno.ths1-11/+19
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-0/+14
2007-06-22Allow emulation of 32bit targets in the MIPS64 capable qemu version.ths1-2/+1
2007-06-12Change 20Kc PRID to a later version.ths1-1/+3
2007-06-09R5k has PX implemented.ths1-2/+2
2007-06-01Update some comments, 64bit FPU support is functional regardless ofths1-4/+7
2007-06-01Add support for 5Kc/5Kf/20Kc, based on a patch by Aurelien Jarno.ths1-2/+50
2007-06-01Allow again FPU for usermode emulation.ths1-1/+6
2007-05-30Fix CPU (re-)selection on reset.ths1-3/+5
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-4/+41
2007-05-11Fix missing status ro mask initialization, thanks Stefan Weil.ths1-0/+1
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-7/+13
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-8/+13
2007-04-11Make SYNCI_Step and CCRes CPU-specific.ths1-0/+16
2007-04-01Actually enable 64bit configuration.ths1-1/+1
2007-03-24One more bit of mips CPU configuration, and support for early 4KEcths1-1/+23
2007-03-21Move mips CPU specific initialization to translate_init.c.ths1-0/+61
2007-03-18MIPS -cpu selection support, by Herve Poussineau.ths1-0/+97