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2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19target-mips: Implement Loongson Multimedia InstructionsRichard Henderson4-4/+1180
Implements all of the COP2 instructions except for the S<cond> family of comparisons. The documentation is unclear for those. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19target-mips: Always evaluate debugging macro argumentsRichard Henderson1-14/+17
this will prevent some of the compilation errors with debugging enabled from creeping back in. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19target-mips: Fix MIPS_DEBUG.Richard Henderson1-36/+38
The macro uses the DisasContext. Pass it around as needed. Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19target-mips: Set opn in gen_ldst_multiple.Richard Henderson1-0/+6
Used by MIPS_DEBUG, when enabled. Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl5-1085/+1162
Add an explicit CPUState parameter instead of relying on AREG0 and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki3-62/+52
This change updates the CPU reset sequence to use a common piece of code that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X not being set where applicable that causes floating-point MADD family instructions (and other instructions from the MIPS IV FP subset) to trap. As compute_hflags is now shared between op_helper.c and translate.c, the function is now moved to a common header. There are no changes to this function. The problem was seen with the 24Kf MIPS32r2 processor in user emulation. The new approach prevents system and user emulation from diverging -- all the hflags state is initialized in one place now. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson1-1/+9
The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27target-mips: add privilege level check to several Cop0 instructionsEric Johnson1-0/+9
The MIPS Architecture Verification Programs (AVPs) check privileged instructions for the required privilege level. These changes are needed to pass the AVP suite. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27mips-linux-user: Always support rdhwr.Richard Henderson1-0/+4
The kernel will emulate this instruction if it's not supported natively. This insn is used for TLS, among other things, and so is required by modern glibc. Signed-off-by: Richard Henderson <rth@twiddle.net> Cc: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27target-mips: Streamline indexed cp1 memory addressing.Richard Henderson1-2/+1
We've already eliminated both base and index being zero. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27Fix order of CVT.PS.S operandsRichard Sandiford1-1/+1
The FS input to CVT.PS.S is the high half and FT is the low half. tcg_gen_concat_i32_i64 takes the low half first, so the operands were in the wrong order. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-27Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford1-2/+2
Read the second input operand of RECIP2.S and RECIP2.PS from FT rather than FD. RECIP2.D is already correct. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-24target-mips: Fix some helper functions (VR54xx multiplication)Stefan Weil1-46/+29
Commits b5dc7732e1cc2fb549e48b7b5d664f2c79628e2e and be24bb4f3007c3e07cbf1934f7e781493d876ab7 optimized the code and removed the correct setting of t0. Fix this. gcc-4.7 detected this bug because parameter arg1 was unused but set in set_HIT0_LO and set_HI_LOT0. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-23target-mips: Enable access to required RDHWR hardware registersMeador Inge1-2/+3
While running in the usermode emulator all of the required* MIPS32r2 RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Note that these registers are still enabled when the MIPS ISA is not release 2. This is OK since the Linux kernel emulates access to them when they are not available in hardware. * There is also the ULR register which is only recommended for full release 2 compliance. Incidentally, accessing this register in the current implementation works fine without flipping its access bit. Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-09MIPS: Correct FCR0 initializationNathan Froyd1-0/+1
This change addresses a problem where QEMU incorrectly traps on floating-point MADD group instructions with SIGILL, at least while emulating MIPS32r2 processors. These instructions use the COP1X major opcode and include ones like: madd.d $f2,$f4,$f2,$f6 Here's Nathan's original analysis of the problem: "QEMU essentially does: d = find_cpu (cpu_string) // get CPU definition fpu_init (env, d) // initialize fpu state (init FCR0, basically) cpu_reset (env) ...and the cpu_reset call clears all interesting state that fpu_init setup, then proceeds to reinitialize all the CP0 registers...but not FCR0." I have verified this change with system emulation running the GDB test suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), there were 55 progressions and no regressions. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-1/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini1-0/+1
Also drop duplicate occurrence of device-hotplug.o. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-06-04Kill off cpu_state_reset()Andreas Färber1-0/+3
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2-4/+12
Turn cpu_init macro into a static inline function returning CPUMIPSState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04target-mips: Use cpu_reset() in do_interrupt()Andreas Färber1-1/+2
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber1-1/+1
Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ify CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the introduction of subclasses for 1.1, due to mips_def_t the reset code could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to CPUClass::reset(). Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling cpu_state_reset(), so that generic code can be converted to call cpu_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-05-19mips: Fix BC1ANY[24]F instructionsRichard Sandiford1-4/+4
There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-05-12target-mips: Remove commented-out function declarationAndreas Färber1-1/+0
There is no function cpu_mips_get_clock(), so drop it. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Stefan Weil <sw@weilnetz.de>
2012-05-03target-mips: Remove unused inline functionStefan Weil1-6/+0
Function set_HILO is not needed anywhere. Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-05-01Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpuBlue Swirl4-2/+148
* 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu: Makefile: Simplify compilation of target-*/cpu.c target-mips: Start QOM'ifying CPU init target-mips: QOM'ify CPU target-m68k: Add QOM CPU subclasses target-m68k: Start QOM'ifying CPU init target-m68k: QOM'ify CPU reset target-m68k: QOM'ify CPU target-sh4: Start QOM'ifying CPU init target-sh4: QOM'ify CPU reset target-sh4: QOM'ify CPU MAINTAINERS: Downgrade target-mips and target-sh4 to Odd Fixes MAINTAINERS: Downgrade target-m68k to Odd Fixes
2012-04-30target-mips: Start QOM'ifying CPU initAndreas Färber2-1/+9
Move code not dependent on mips_def_t from cpu_mips_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30target-mips: QOM'ify CPUAndreas Färber4-1/+139
Embed CPUMIPSState as first member of QOM MIPSCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-28target-mips: Move definition of uint_fast{8, 16}_t to osdep.hAndreas Färber1-7/+0
osdep.h is included via qemu-common.h. Prepares for use of [u]int_fast*_t types in softfloat code. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Ben Taylor <bentaylor.solx86@gmail.com> Cc: Aurélien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Tested-by: Bernhard Walle <bernhard@bwalle.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-15target-mips: Fix type cast for w64 (uintptr_t)Stefan Weil1-1/+1
This changes nothing for other hosts. Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-10/+8
Use uintptr_t instead of void * or unsigned long in several op related functions, env->mem_io_pc and GETPC() macro. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07Replace Qemu by QEMU in commentsStefan Weil1-1/+1
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07Replace Qemu by QEMU in internal documentationStefan Weil1-2/+2
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24target-mips: Add compiler attribute to some functions which don't returnStefan Weil2-3/+4
helper_raise_exception_err does not return, nor do helper_raise_exception and do_unaligned_access. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-mips: Don't overuse CPUStateAndreas Färber5-274/+274
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber2-3/+3
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-08Spelling fixes in comments (it's -> its)Stefan Weil1-1/+1
* it's -> its (fixed for all files) * dont -> don't (only fixed in a line which was touched by the previous fix) * distrub -> disturb (fixed in the same line) Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-02-28target-mips: Clean includesStefan Weil1-7/+0
Remove some include statements which are not needed. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2011-12-14Fix spelling in comments, documentation and messagesStefan Weil1-1/+1
accidently->accidentally annother->another choosen->chosen consideres->considers decriptor->descriptor developement->development paramter->parameter preceed->precede preceeding->preceding priviledge->privilege propogation->propagation substraction->subtraction throught->through upto->up to usefull->useful Fix also grammar in posix-aio-compat.c Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-02fix spelling in target sub directoryDong Xu Wang2-2/+2
Cc: Richard Henderson <rth@twiddle.net> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-4/+3
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06mips: Support the MT TCStatus IXMT irq disable flagEdgar E. Iglesias1-0/+4
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Add MT halting and waking of VPEsEdgar E. Iglesias2-4/+129
+ some partial support for TC's. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Initialize MT state at resetEdgar E. Iglesias1-0/+26
Only TC0 on VPE0 is active after reset. All other VPEs and TCs start in sleep. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Default to using one VPE and one TC.Edgar E. Iglesias1-1/+1
Boards can override the setup if needed. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Enable VInt interrupt mode for the 34KfEdgar E. Iglesias1-1/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Correct VInt vector generationEdgar E. Iglesias1-3/+3
1. The pending need to pass the Status IM gating. 2. The priority is from seven (highest prio) down to zero. QEMU was doing the opposite. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06mips: Correct IntCtl write mask for VIntEdgar E. Iglesias1-1/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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