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AgeCommit message (Expand)AuthorFilesLines
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber3-2/+6
2013-02-16target-mips: Introduce QOM realizefn for MIPSCPUAndreas Färber3-2/+20
2013-01-31target-mips: enable access to DSP ASE if implementedPetar Jovanovic1-4/+2
2013-01-31target-mips: Unfuse {,N}M{ADD,SUB}.fmtRichard Sandiford1-8/+17
2013-01-31target-mips: Sign-extend the result of LWRRichard Sandiford1-0/+1
2013-01-31target-mips: Fix signedness of loads in MIPS16 RESTOREsRichard Sandiford1-1/+1
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno3-126/+87
2013-01-31target-mips: use DSP unions for reduction add instructionsAurelien Jarno1-16/+14
2013-01-31target-mips: use DSP unions for unary DSP operatorsAurelien Jarno1-82/+42
2013-01-31target-mips: use DSP unions for binary DSP operatorsAurelien Jarno1-268/+116
2013-01-31target-mips: add unions to access DSP elementsAurelien Jarno1-0/+22
2013-01-31target-mips: generate a reserved instruction exception on CPU without DSPAurelien Jarno1-2/+10
2013-01-31target-mips: copy insn_flags in DisasContextAurelien Jarno1-381/+381
2013-01-31target-mips: fix DSP loads with rd = 0Aurelien Jarno1-5/+0
2013-01-15exec: Return CPUState from qemu_get_cpu()Andreas Färber1-3/+8
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber2-10/+15
2013-01-15target-mips: Clean up mips_cpu_map_tc() documentationAndreas Färber1-5/+9
2013-01-15cpu: Move nr_{cores,threads} fields to CPUStateAndreas Färber1-3/+5
2013-01-08target-mips: Fix helper and tests for dot/cross-dot product instructionsPetar Jovanovic1-1/+1
2013-01-08target-mips: Replace macros by inline functionsStefan Weil1-18/+24
2013-01-08target-mips: Allow DSP access to be disabled once enabled.Eric Johnson1-1/+1
2013-01-01target-mips: Use EXCP_SC rather than a magic number陳韋任 (Wei-Ren Chen)1-3/+2
2013-01-01target-mips: Make repl_ph to sign extend to target-longJovanovic, Petar1-1/+2
2013-01-01Fix my email addressDongxue Zhang1-1/+1
2013-01-01target-mips: Remove semicolon from macro definitionStefan Weil1-1/+1
2013-01-01target-mips: Fix for helpers for EXTR_* instructionsPetar Jovanovic1-35/+10
2013-01-01target-mips: Fix incorrect reads and writes to DSPControl registerPetar Jovanovic1-0/+8
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini4-11/+11
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-7/+1
2012-12-08Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl1-9/+10
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-12-06target-mips: Fix incorrect shift for SHILO and SHILOVPetar Jovanovic1-8/+9
2012-12-06target-mips: Fix incorrect code and test for INSVPetar Jovanovic1-1/+1
2012-11-24target-mips: remove POOL48A from the microMIPS decodingAurelien Jarno1-1/+0
2012-11-24target-mips: Clean up microMIPS32 major opcode陳韋任 (Wei-Ren Chen)1-7/+17
2012-11-24target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)1-0/+17
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-15target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)1-1/+1
2012-11-11target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson1-7/+11
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-11-05target-mips: use ULL for 64 bit constantsBlue Swirl1-2/+2
2012-11-01Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori1-5/+6
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