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2012-10-31target-mips: don't flush extra TLB on permissions upgradeAurelien Jarno1-5/+23
2012-10-31target-mips: fix TLBR wrt SEGMaskAurelien Jarno1-0/+6
2012-10-31target-mips: use deposit instead of hardcoded versionAurelien Jarno1-28/+4
2012-10-31target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno1-48/+37
2012-10-31target-mips: implement movn/movz using movcondAurelien Jarno1-15/+12
2012-10-31target-mips: don't use local temps for store conditionalAurelien Jarno1-5/+6
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno3-159/+62
2012-10-31target-mips: simplify load/store microMIPS helpersAurelien Jarno1-64/+9
2012-10-31target-mips: optimize load operationsAurelien Jarno1-4/+12
2012-10-31target-mips: cleanup load/store operationsAurelien Jarno1-64/+35
2012-10-31target-mips: restore CPU state after an FPU exceptionAurelien Jarno1-90/+95
2012-10-31target-mips: use softfloat constants when possibleAurelien Jarno1-48/+44
2012-10-31target-mips: cleanup float to int conversion helpersAurelien Jarno1-39/+79
2012-10-31target-mips: fix FPU exceptionsAurelien Jarno1-13/+19
2012-10-31target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno1-63/+10
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno3-105/+64
2012-10-31target-mips: do not save CPU state when using retranslationAurelien Jarno1-20/+0
2012-10-31target-mips: correctly restore btarget upon exceptionAurelien Jarno1-0/+11
2012-10-31target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno1-36/+0
2012-10-31target-mips: Change TODO fileJia Liu1-2/+1
2012-10-31target-mips: Add ASE DSP processorsJia Liu1-0/+52
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu3-0/+995
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu3-0/+635
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu3-0/+311
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu3-0/+1499
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu3-0/+618
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu3-3/+1812
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu1-0/+88
2012-10-31target-mips: Add ASE DSP branch instructionsJia Liu1-0/+36
2012-10-31Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu1-27/+95
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu3-2/+47
2012-10-31target-mips: Add ASE DSP internal functionsJia Liu2-1/+1064
2012-10-28target-mips: Use TCG registers for the FPU.Richard Henderson1-42/+54
2012-10-28target-mips: rename helper flagsAurelien Jarno1-53/+53
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity3-18/+18
2012-10-17target-mips: Pass MIPSCPU to mips_vpe_sleep()Andreas Färber1-3/+7
2012-10-17target-mips: Pass MIPSCPU to mips_tc_sleep()Andreas Färber1-3/+5
2012-10-17target-mips: Pass MIPSCPU to mips_vpe_is_wfi()Andreas Färber1-4/+8
2012-10-17target-mips: Pass MIPSCPU to mips_tc_wake()Andreas Färber1-3/+8
2012-10-17target-mips: Clean up other_cpu in helper_{d,e}vpe()Andreas Färber1-14/+14
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
2012-09-19target-mips: Implement Loongson Multimedia InstructionsRichard Henderson4-4/+1180
2012-09-19target-mips: Always evaluate debugging macro argumentsRichard Henderson1-14/+17
2012-09-19target-mips: Fix MIPS_DEBUG.Richard Henderson1-36/+38
2012-09-19target-mips: Set opn in gen_ldst_multiple.Richard Henderson1-0/+6
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl5-1085/+1162
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki3-62/+52
2012-08-27target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson1-1/+9
2012-08-27target-mips: add privilege level check to several Cop0 instructionsEric Johnson1-0/+9
2012-08-27mips-linux-user: Always support rdhwr.Richard Henderson1-0/+4
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