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2010-07-25mips: more fixes to the MIPS interrupt glue logicAurelien Jarno4-15/+21
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the interrupt logic to cpu-exec.c. Remove the remaining useless code and fix software interrupts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-24mips: Correct MIPS interrupt glue logic for icountEdgar E. Iglesias2-14/+0
When hw interrupt pending bits in CP0_Cause are set, the CPU should see the hw interrupt line as active. The CPU may or may not take the interrupt based on internal state (global irq mask etc) but the glue logic shouldn't care. This fixes MIPS external hw interrupts in combination with -icount. Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-17target-mips: fix xtlb exception for loongsonAurelien Jarno1-2/+4
Loongson 2E and 2F use the same entry for xtlb and tlb exception, at offset 0x000. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-11target-mips: add loongson 2E & 2F integer instructionsAurelien Jarno1-0/+271
This patch adds support for loongson 2E & 2F instructions. They are the same instructions, but differ by the opcode encoding. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2-7/+7
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03remove unused stuff from */exec.hPaolo Bonzini2-9/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-01target-mips: add Loongson support prefetchAurelien Jarno1-35/+43
Loongson CPU uses a load to zero register for prefetch. Emulate it as a NOP. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-mips: split load and storeAurelien Jarno1-155/+183
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-30target-mips: fix DINSU instructionAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29target-mips: enable movn/movz on loongson 2E & 2FAurelien Jarno1-1/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29MIPS: Initial support of fulong mini pc (CPU definition)Huacai Chen2-0/+39
Signed-off-by: Huacai Chen <zltjiangshi@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: Fix compilationStefan Weil1-1/+1
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32. Cc: Nathan Froyd <froydnj@codesourcery.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: add microMIPS exception handler supportNathan Froyd2-6/+16
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception handlers. The ISA mode is selectable via a user-writable CP0.Config3 flag. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: microMIPS ASE supportNathan Froyd4-5/+2531
Add instruction decoding for the microMIPS ASE. All we do is decode and then forward to the existing gen_* routines. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: mips16 cleanupsNathan Froyd1-7/+17
Change code handling mips16-specific branches to use ISA-neutral special opcodes. Since there are several places where the delay slot requirements for microMIPS branches differ from mips16 branches, using opcodes is easier than checking hflags, then checking mips16 vs. microMIPS. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: refactor c{, abs}.cond.fmt insnsNathan Froyd1-83/+81
Move all knowledge about coprocessor-checking and register numbering into the gen_cmp* helper functions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: move FP FMT comments closer to the definitionsAurelien Jarno1-14/+14
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09target-mips: define constants for magic numbersNathan Froyd1-142/+295
Add FMT_* constants for the floating-point format field in opcodes and tweak a few places to use them. Add enums for various invocations of FOP and tweak gen_farith and its lone caller accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-08target-mips: break out [ls][wd]c1 and rdhwr insn generationNathan Froyd1-47/+59
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05target-mips: Remove duplicate CPU log.Richard Henderson1-6/+0
Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09target-mips: Fix format specifiers for fpu_fprintfStefan Weil1-14/+20
In the previous patch which introduced fprintf_function to allow parameter checking by gcc some compiler warnings remained unfixed. These warnings are fixed here. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08target-mips: Fix one more format specifier for cpu_fprintfStefan Weil1-1/+3
env->bcond must be printed using TARGET_FMT_ld. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08remove TARGET_* defines from translate-all.cPaolo Bonzini1-0/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-17Large page TLB flushPaul Brook1-3/+4
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-13target-mips: update address space definitionsAurelien Jarno1-4/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Target specific usermode cleanupPaul Brook2-2/+14
Disable various target specific code that is only relevant to system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-4/+2
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson1-0/+4
Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-04target-mips: use newer logical opsAurelien Jarno1-8/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02target-mips: use setcond when possibleAurelien Jarno1-77/+20
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23target-mips: fix ROTR and DROTR by zeroNathan Froyd1-0/+4
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23target-mips: fix CpU exception for coprocessor 0Nathan Froyd1-1/+1
When we signal a CpU exception for coprocessor 0, we should indicate that it's for coprocessor 0 instead of coprocessor 1. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23target-mips: remove useless sign extensionAurelien Jarno1-2/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06target-mips: don't call cpu_loop_exit() from helper.cAurelien Jarno3-8/+22
In helper.c AREG0 may not correspond do env, so it's not possible to call cpu_loop_exit() here. Call it from op_helper.c instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-19kill regs_to_env and env_to_regsPaolo Bonzini1-8/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-17target-mips: No MIPS16 support for 4Kc, 4KEc coresStefan Weil1-3/+3
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487. 4Kc and 4KEc don't support MIPS16. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-16target-mips: 4Kc, 4KEc cores do not support MIPS16Stefan Weil1-3/+3
4Kc, 4KEc cores do not support MIPS16, so not only the CP0_Config1 had to be fixed (see previous patch), but also MIPS16 instructions must not be executed. (Hint from Nathan Froyd, thanks). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: fix user-mode emulation startupNathan Froyd2-8/+8
Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: set Config1.CA for MIPS16-aware CPUsNathan Froyd1-9/+18
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add copyright notice for mips16 workNathan Froyd2-1/+1
Also cross off mips16 ASE in TODO. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add mips16 instruction decodingNathan Froyd1-9/+1063
There's no good way to add this incrementally, so we do it all at once. The only changes to shared code are in handle_delay_slot. We need to flip ISAMode when doing a jump-and-exchange. We also need to set ISAMode the low bit of the target address for jump-to-register. Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT, make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want basic information about a branch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add enums for MIPS16 opcodesNathan Froyd1-0/+112
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: split out delay slot handlingNathan Froyd1-55/+79
Move delay slot handling to common code whose invocation can be controlled from gen_intermediate_code_internal. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add gen_base_offset_addrNathan Froyd1-24/+16
This is a common pattern in existing code. We'll also use it to implement the mips16 SAVE/RESTORE instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: make gen_compute_branch 16/32-bit-awareNathan Froyd1-7/+8
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: move ROTR and ROTRV inside gen_shift_{imm, }Nathan Froyd1-139/+148
It's easier to implement mips16 shift instructions if we're not examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV and do the special-case handling of SRL and SRLV inside decode_opc. Likewise for their 64-bit counterparts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: change interrupt bits to be mips16-awareNathan Froyd2-24/+44
We need to stash the operating mode into the low bit of the error PC and restore it on return from interrupts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add new HFLAGs for JALX and 16/32-bit delay slotsNathan Froyd1-19/+28
We create separate masks for the "basic" branch hflags and the "extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or of those two. This is done to avoid churning the codebase in lots of different places. We also make the execution mode an hflag under MIPS_HFLAG_TMASK Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: use physical address in lladdrAurelien Jarno3-28/+61
Currently the ll/sc instructions use the virtual address in both user and system mode. Use the physical address insteead in system mode. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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