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AgeCommit message (Expand)AuthorFilesLines
2007-04-04Fix code formatting.ths1-66/+66
2007-04-02MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths1-2/+9
2007-04-02Build fix for 64bit machines. (This is still not correct mul/div handling.)ths1-6/+12
2007-04-01Actually enable 64bit configuration.ths8-38/+35
2007-04-01MIPS64 configurations.ths1-2/+0
2007-03-31Malta CBUS UART support.ths1-1/+1
2007-03-30Update mips TODO.ths1-5/+1
2007-03-30Fix typo, suggested by Ben Taylor.ths1-1/+1
2007-03-30Squash logic bugs while they are fresh...ths1-1/+0
2007-03-30Sanitize mips exception handling.ths5-73/+55
2007-03-24One more bit of mips CPU configuration, and support for early 4KEcths1-1/+23
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths5-26/+66
2007-03-21Move mips CPU specific initialization to translate_init.c.ths3-40/+61
2007-03-19Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.ths1-5/+13
2007-03-19Define gen_intermediate_code_internal as "static inline".ths1-2/+3
2007-03-19SPARC host fixes, by Ben Taylor.ths1-10/+0
2007-03-18Fix BD flag handling, cause register contents, implement some more bitsths2-4/+17
2007-03-18MIPS -cpu selection support, by Herve Poussineau.ths4-33/+104
2007-03-17Note FPU enable/disable issue.ths1-0/+2
2007-03-02MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths3-0/+17
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths7-101/+65
2007-02-27Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths2-30/+17
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths5-43/+36
2007-02-18Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths3-3/+3
2007-02-02Update MIPS TODO.ths1-4/+2
2007-02-02Sparc arm/mips/sparc register patch, by Martin Bochnig.ths1-0/+10
2007-01-24EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths3-21/+6
2007-01-24Reworking MIPS interrupt handling, by Aurelien Jarno.ths4-51/+18
2007-01-23Implementing dmfc/dmtc.ths4-86/+1434
2007-01-22Update TODO.ths1-3/+4
2007-01-22Fix PageMask handling, second part.ths3-16/+36
2007-01-21TLB address wraparound hopefully fixed now.ths1-1/+0
2007-01-21Bring TLB / PageSize handling in line with real hardware behaviour.ths2-25/+5
2007-01-19Note more issues.ths1-6/+17
2007-01-17Keep track of mips related issues.ths1-0/+17
2007-01-03moved invalidate_tlb() to helper.c as a work around for gcc 3.2.2 bug - suppr...bellard3-45/+45
2007-01-01Fix bad data type.ths1-1/+1
2007-01-01Fix lwl/lwr for 64bit emulation, also debug output spec for 64bit emulation.ths1-24/+26
2007-01-01Simplify code and fix formatting.ths1-6/+6
2006-12-23Check ELF binaries for machine type and endianness.ths1-0/+2
2006-12-23Use memory barriers in FORCE_RET / RETURN.ths1-2/+2
2006-12-21Scrap SIGN_EXTEND32.ths5-74/+71
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths11-202/+949
2006-12-16Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto.ths1-0/+1
2006-12-10Handle invalid accesses as SIGILL for mips/mipsel userland emulation.ths2-0/+10
2006-12-07Fix build of MIPS target without FPU support.ths2-0/+26
2006-12-07Fix reset handling, CP0 isn't enabled by default (a fact which doesn'tths2-38/+31
2006-12-07Simplify mask construction.ths1-2/+2
2006-12-06Update copyright notice.ths1-0/+1
2006-12-06Add MIPS32R2 instructions, and generally straighten out the instructionths7-591/+2235
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