summaryrefslogtreecommitdiff
path: root/target-ppc/helper.h
AgeCommit message (Expand)AuthorFilesLines
2014-03-05target-ppc: Altivec 2.07: Unpack Signed Word InstructionsTom Musta1-0/+2
2014-03-05target-ppc: Altivec 2.07: Pack Doubleword InstructionsTom Musta1-0/+4
2014-03-05target-ppc: Altivec 2.07: Vector Min/Max Doubleword InstructionsTom Musta1-0/+4
2014-03-05target-ppc: Altivec 2.07: Vector Population Count InstructionsTom Musta1-0/+4
2014-03-05target-ppc: Altivec 2.07: Add Vector Count Leading ZeroesTom Musta1-0/+5
2014-03-05target-ppc: Altivec 2.07: vmuluw InstructionTom Musta1-0/+1
2014-03-05target-ppc: Altivec 2.07: Multiply Even/Odd Word InstructionsTom Musta1-0/+4
2014-03-05target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword ModuloTom Musta1-0/+2
2014-03-05target-ppc: Add ISA 2.06 ftsqrtTom Musta1-0/+1
2014-03-05target-ppc: Add ISA 2.06 ftdiv InstructionTom Musta1-0/+2
2014-03-05target-ppc: Add ISA 2.06 fcfid[u][s] InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add ISA2.06 Float to Integer InstructionsTom Musta1-0/+4
2014-03-05target-ppc: Add ISA 2.06 divwe[o] InstructionsTom Musta1-0/+1
2014-03-05target-ppc: Add ISA 2.06 divweu[o] InstructionsTom Musta1-0/+1
2014-03-05target-ppc: Add ISA2.06 divde[o] InstructionsTom Musta1-0/+1
2014-03-05target-ppc: Add ISA2.06 divdeu[o] InstructionsTom Musta1-0/+1
2014-03-05target-ppc: Add ISA2.06 bpermd InstructionTom Musta1-0/+1
2014-03-05target-ppc: Scalar Non-Signalling ConversionsTom Musta1-0/+2
2014-03-05target-ppc: Scalar Round to Single PrecisionTom Musta1-0/+1
2014-03-05target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdspTom Musta1-0/+2
2014-03-05target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-AddsTom Musta1-0/+8
2014-03-05target-ppc: VSX Stage 4: add xsrsqrtespTom Musta1-0/+1
2014-03-05target-ppc: VSX Stage 4: Add xssqrtspTom Musta1-0/+1
2014-03-05target-ppc: VSX Stage 4: Add xsrespTom Musta1-0/+1
2014-03-05target-ppc: VSX Stage 4: Add xsdivspTom Musta1-0/+1
2014-03-05target-ppc: VSX Stage 4: Add xsmulspTom Musta1-0/+1
2014-03-05target-ppc: VSX Stage 4: Add xsaddsp and xssubspTom Musta1-0/+3
2014-03-05target-ppc: Add VSX Rounding InstructionsTom Musta1-0/+15
2014-03-05target-ppc: Add VSX ISA2.06 Integer Conversion InstructionsTom Musta1-0/+22
2014-03-05target-ppc: Add VSX Floating Point to Floating Point Conversion InstructionsTom Musta1-0/+4
2014-03-05target-ppc: Add VSX Vector Compare InstructionsTom Musta1-0/+6
2014-03-05target-ppc: Add VSX xmax/xmin InstructionsTom Musta1-0/+6
2014-03-05target-ppc: Add VSX xscmp*dp InstructionsTom Musta1-0/+2
2014-03-05target-ppc: Add VSX ISA2.06 Multiply Add InstructionsTom Musta1-0/+24
2014-03-05target-ppc: Add VSX ISA2.06 xtsqrt InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xtdiv InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xrsqrte InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xsqrt InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xre InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xdiv InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xmul InstructionsTom Musta1-0/+3
2014-03-05target-ppc: Add VSX ISA2.06 xadd/xsub InstructionsTom Musta1-0/+9
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-5/+5
2013-04-26target-ppc: emulate cmpb instructionAurelien Jarno1-0/+1
2013-04-26target-ppc: optimize fabs, fnabs, fnegAurelien Jarno1-3/+0
2013-03-22target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson1-1/+0
2013-02-23target-ppc: Use mul*2 in mulh* insnsRichard Henderson1-2/+0
2013-02-01PPC: Unify dcbzl code pathAlexander Graf1-2/+1
2013-01-07PPC: Bring EPR support closer to realityAlexander Graf1-1/+0
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2