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2014-11-20target-ppc: Altivec's mtvscr Decodes Wrong RegisterTom Musta1-1/+1
The Move to Vector Status and Control Register (mtvscr) instruction uses VRB as the source register. Fix the code generator to correctly decode the VRB field. That is, use "rB(ctx->opcode)" instead of "rD(ctx->opcode)". Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04target-ppc: Fix Altivec Round OpcodesTom Musta1-6/+6
Correct the opcodes for the vrfim, vrfin and vrfiz instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04ppc: do not look at the MMU index to detect PR/HV modePaolo Bonzini1-88/+77
The MMU index is an internal detail that should not be needed by the translator (except to generate loads and stores). Look at the MSR directly. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard1-10/+6
This patch remove limitation for fc[tf]id[*] on 32 bits targets and add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64 Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04ppc: compute mask from BI using right shiftPaolo Bonzini1-3/+3
This will match the code we use in fpu_helper.c when we flip CRF_* bit-endianness. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-11-04ppc: rename gen_set_cr6_from_fpscrPaolo Bonzini1-7/+7
It sets CR1, not CR6 (and the spec agrees). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Implement mulldo with TCGTom Musta1-2/+14
Optimize mulldo by using the muls2_i64 operation rather than a helper. Eliminate the obsolete helper code. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Clean up mullwoTom Musta1-8/+3
Simplify the implementation of mullwo. For 64 bit CPUs, the result is the concatenation of the upper and lower parts of the muls2_i32 operation, which may be slightly better than deposit. For 32 bit CPUs, the lower part of the muls_i32 operation is moved into the target GPR. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Clean Up mullwTom Musta1-3/+2
Eliminate the unecessary ext32s TCG operation and make the multiplication operation explicitly 32 bit. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta1-22/+34
Optimize the special case of rlwnm where MB=0 and ME=31. This can be implemented using a ROTL. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta1-0/+6
Optimize the special case of rlwinm where MB=0 and ME=31. This can be implemented as a 32-bit ROTL. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Special Case of rlwimi Should Use DepositTom Musta1-6/+3
The special case of rlwimi where MB <= ME and SH = 31-ME can be implemented with a single TCG deposit operation. This replaces the less general case of SH = MB = 0 and ME = 31. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: srawiTom Musta1-1/+1
For 64 bit implementations, the special case of a shift by zero should result in the sign extension of the least significant 32 bits of the source GPR (not a direct copy of the 64 bit source GPR). Example: R3 A6212433228F41DC srawi 3,3,0 R3 expected : 00000000228F41DC R3 actual : A6212433228F41DC (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: mullwTom Musta1-0/+11
For 64-bit implementations, the mullw result is the 64 bit product of the sign-extended least significant 32 bits of the source registers. Fix the code to properly sign extend the source operands and produce a 64 bit product. Example: R3 00000000002F37A0 R4 41C33D242F816715 mullw 3,3,4 R3 expected : 0008C3146AE0F020 R3 actual : 000000006AE0F020 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: mullwoTom Musta1-0/+9
On 64-bit implementations, the mullwo result is the 64 bit product of the signed 32 bit operands. Fix the implementation to properly deposit the upper 32 bits into the target register. Example: R3 0407DED115077586 R4 53778DF3CA992E09 mullwo 3,3,4 R3 expected : FB9D02730D7735B6 R3 actual : 000000000D7735B6 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: rlwimiTom Musta1-5/+7
The rlwimi specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Also fix the special case of MB=31 and ME=0 to copy the entire contents of the source GPR. Examples: R3 FFFFFFFFFFFFFFF0 rlwimi 3,3,29,14,1 R3 expected : 1FFFFFFE3FFFFFFE R3 actual : 000000003FFFFFFE (without this patch) R3 ED7EB4DD824F0853 rlwimi 3,3,10,31,0 R3 expected : 3C214E09024F0853 R3 actual : 00000000024F0853 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: rlwnmTom Musta1-9/+9
The rlwnm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Example: R3 = 0000000000000002 R4 = 7FFFFFFFFFFFFFFF rlwnm 3,3,4,31,16 R3 expected : 0000000100000001 R3 actual : 0000000000000001 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: rlwinmTom Musta1-5/+3
The rlwinm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Example: R3 = F7487D82EC6F75DF rlwinm 3,3,5,12,4 R3 expected : 8DEEBBFD880EBBFD R3 actual : 00000000880EBBFD (without this fix) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-27target-ppc: Remove unused gen_qemu_ld8s()Peter Maydell1-5/+0
The gen_qemu_ld8s() function is unused; remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-27target-ppc: Remove unused IMM and d extract helpersPeter Maydell1-3/+0
Remove the definition of the IMM and d extract helpers; these seem to have been added as part of the initial PPC support in 2003 but never actually used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-27target-ppc: fixed translation of mcrxr instructionSorav Bansal1-2/+3
Fixed bug in gen_mcrxr() in target-ppc/translate.c: The XER[SO], XER[OV], and XER[CA] flags are stored in the least significant bit (bit 0) of their respective registers. They need to be shifted left (by their respective offsets) to generate the final XER value. The old translation code for the 'mcrxr' instruction was assuming that the flags are stored in bit 2, and was shifting them right (incorrectly) Signed-off-by: Sorav Bansal <sbansal@cse.iitd.ernet.in> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy1-0/+7
This adds an FSCR (Facility Status and Control Register) SPR. This defines names for FSCR bits. This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU). This registers an interrupt vector for it at 0xF60 as PowerISA defines. This adds a TCG helper_fscr_facility_check() helper to raise an exception if the facility is not enabled. It updates the interrupt cause field in FSCR. This adds a TCG translation block generation code. The helper may be used for HFSCR too as it has the same format. The helper raising FU exceptions is not used by this patch but will be in the next ones. This adds gen_update_current_nip() to update NIP in DisasContext. This helper is not used now and will be called before checking for a condition for throwing an FU exception. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Fix Temporary Variable Leak in bctarTom Musta1-1/+1
Fix a temporary variable leak detected in the bctar instruction: Opcode 13 10 11 (4d910460) leaked temporaries Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Merge 32 and 64 bit SPE emulationAlexander Graf1-579/+132
Today we have a lot of conditional code in the SPE emulation depending on whether we have 64bit GPRs or not. Unfortunately the assumption that we can just recycle the 64bit GPR implementation is wrong. Normal SPE implementations maintain the upper 32 bits on all non-SPE instructions which then only modify the low 32 bits. However all instructions we model that adhere to the normal SF based switching don't care whether they operate on 32 or 64 bit registers and just always use the full 64 bits. So let's remove that dubious SPE optimization and revert everything to the same code path the 32bit target code was taking. That way we get rid of differences between the two implementations, but will get a slight performance hit when emulating SPE instructions. This fixes SPE emulation with qemu-system-ppc64 for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: SPE: Fix high-bits bitmaskAlexander Graf1-2/+2
The SPE emulation code wants to access the highest 32bits of a 64bit register and uses the andi TCG instruction for that. Unfortunately it masked with the wrong mask. Fix the mask to actually cover the upper 32 bits. This fixes simple multiplication tests with SPE guests for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Allow little-endian user mode.Doug Kwan1-91/+60
This allows running PPC64 little-endian in user mode if target is configured that way. In PPC64 LE user mode we set MSR.LE during initialization. Signed-off-by: Doug Kwan <dougkwan@google.com> Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Fix popcntb Opcode BugTom Musta1-1/+1
The popcntb instruction is erroneously encoded with opcode extension (opc1,opc2) = (0x03,0x03). Bits 21-30 of popcntb are 122 = 0b00011-0b11010 and therefore this should be encoded as (opc1,opc2) = (0x1A, 0x03). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add dcbtls emulationAlexander Graf1-0/+12
The dcbtls instruction is able to lock data inside the L1 cache. Unfortunately we don't emulate any caches, so we have to tell the guest that its locking attempt failed. However, by implementing the instruction we at least don't give the guest a program exception which it definitely does not expect. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Fail on leaking temporariesAlexander Graf1-0/+7
When QEMU gets compiled with --enable-debug-tcg we can check for temporary leakage. Implement the necessary target code for this and fail emulation when we hit a leakage. This hopefully ensures that we don't get new leaks. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Fix TCG chunks that don't free their tempsAlexander Graf1-0/+7
We want to make sure that every instruction cleans up after itself and clears every temporary it allocated. While checking whether this is already the case, I came across a few cases where it isn't. This patch fixes every translation I found that doesn't free their allocated temporaries. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Shift SignificandTom Musta1-0/+10
Add emulation of the PowerPC Decimal Floating Point Shift Significand Left Immediate (dscli[q][.]) and DFP Shift Significant Right Immediate (dscri[q][.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Insert Biased ExponentTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Insert Biased Exponent instructions diex[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Extract Biased ExponentTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Extract Biased Exponent instructions dxex[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Encode BCD to DPDTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Encode Binary Coded Decimal to Densely Packed Decimal instructions denbcd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Decode DPD to BCDTom Musta1-0/+4
Add emulation of the Power PC Decimal Floating Point Decode Densely Packed Decimal to Binary Coded Decimal instructions ddedpd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Convert to FixedTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Convert to Fixed instructions dctfix[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Convert to FixedTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Convert to Fixed instructions dctfix[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce Round to DFP Short/LongTom Musta1-0/+4
Add emulation of the PowerPC Round to DFP Short (drsp[.]) and Round to DFP Long (drdpq[.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Convert to Long/ExtendedTom Musta1-0/+4
Add emulation of the PowerPC Convert to DFP Long (dctdp[.]) and Convert to DFP Extended (dctqpq[.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Round to IntegerTom Musta1-0/+8
Add emulation of the PowerPC Decimal Floating Point (DFP) Round to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP Integer Without Inexact (drintn[q][.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP ReroundTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Reround instructions drrnd[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP QuantizeTom Musta1-0/+8
Add emulation of the PowerPC Decimal Floating Point Quantize instructions dquai[q][.] and dqua[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test SignificanceTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Test Significance instructions dtstsf[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test ExponentTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Test Exponent instructions dtstex[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test Data GroupTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Test Data Group instructions dtstdg[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP Test Data ClassTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Test Data Class instructions dtstdc[q][.]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP ComparesTom Musta1-0/+8
Add emulation of the PowerPC Decimal Floating Point Compare instructions dcmpu[q] and dcmpo[q]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP DivideTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Divide instructions ddiv[q][.] Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce DFP MultiplyTom Musta1-0/+4
Add emulation of the PowerPC Decimal Floating Point Multiply instructions dmul[q][.] Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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