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path: root/target-ppc/translate_init.c
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2013-07-23gdbstub: Change gdb_register_coprocessor() argument to CPUStateAndreas Färber1-7/+8
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber1-0/+3
Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+8
This moves setting the Program Counter from gdbstub into target code. Use vaddr type as upper-bound replacement for target_ulong. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-11target-ppc: Add POWER8 v1.0 CPU modelPrerna Saxena1-0/+34
This patch adds CPU PVR definition for POWER8, and enables QEMU to launch guests on POWER8 hardware. Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org> Reviewed-by: Andreas Farber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11e600 core for MPC86xx processorsJulio Guerra1-0/+125
MPC86xx processors are based on the e600 core, which is not the case in qemu where it is based on the 7400 processor. This patch creates the e600 core and instantiates the MPC86xx processors based on it. Therefore, adding the high BATs, the SPRG 4..7 registers, which are e600-specific [1], and a HW MMU model (as 7400). This allows to define the MPC8610 processor too. Tested with a kernel using the HW TLB misses. [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf Signed-off-by: Julio Guerra <guerr@julio.in> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-09cpu: Move reset logging to CPUStateAndreas Färber1-5/+0
x86 was using additional CPU_DUMP_* flags, so make that configurable in CPUClass::reset_dump_flags. This adds reset logging for alpha, unicore32 and xtensa. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber1-1/+1
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> [AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-01PPC: Ignore writes to L2CRAlexander Graf1-11/+11
The L2CR register contains a number of bits that either impose configuration which we can't deal with or mean "something is in progress until the bit is 0 again". Since we don't model the former and we do want to accomodate guests using the latter semantics, let's just ignore writes to L2CR. That way guests always read back 0 and are usually happy with that. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Introduce an alias cache for faster lookupsAlexander Graf1-5/+27
When running QEMU with "-cpu ?" we walk through every alias for every target CPU we know about. This takes several seconds on my very fast host system. Let's introduce a class object cache in the alias table. Using that we don't have to go through the tedious work of finding our target class. Instead, we can just go directly from the alias name to the target class pointer. This patch brings -cpu "?" to reasonable times again. Before: real 0m4.716s After: real 0m0.025s Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc: Introduce unrealizefn for PowerPCCPUAndreas Färber1-1/+15
Use it to clean up the opcode table, resolving a former TODO from Jocelyn. Also switch from malloc() to g_malloc(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01ppc: do not register IABR SPR twice for 603eHervé Poussineau1-5/+0
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E(). Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc: Drop redundant flags assignments from CPU familiesAndreas Färber1-45/+0
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in some places for macrofied assignment to insns_flags2 field. PPC_NONE is defined as zero though and QOM classes are zero-initialized, so drop any pcc->insns_flags2 = PPC_NONE; assignments. PPC_NONE itself is still in use in translate.c. Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-2/+0
This allows to move the call into CPUState's realizefn. Therefore move the stub into libqemustub.a. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-0/+2
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-06target-ppc: Add read and write of PPR SPRAnton Blanchard1-0/+4
Recent Linux kernels save and restore the PPR across exceptions so we need to handle it. Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: add instruction flags for Book I 2.05Aurelien Jarno1-1/+1
.. and enable it on POWER7 CPU. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Add more stubs for POWER7 PMU registersDavid Gibson1-0/+12
In addition to the performance monitor registers found on nearly all 6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an extra control register (MMCRA). This patch adds stub support for them to qemu - the registers won't do anything, but with this change won't cause illegal instruction traps accessing them. They're also registered with their ONE_REG ids, so their value will be kept in sync with KVM where appropriate. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26pseries: Fixes and enhancements to L1 cache propertiesDavid Gibson1-0/+3
PAPR requires that the device tree's CPU nodes have several properties with information about the L1 cache. We already create two of these properties, but with incorrect names - "[id]cache-block-size" instead of "[id]-cache-block-size" (note the extra hyphen). We were also missing some of the required cache properties. This patch adds the [id]-cache-line-size properties (which have the same values as the block size properties in all current cases). We also add the [id]-cache-size properties. Adding the cache sizes requires some extra infrastructure in the general target-ppc code to (optionally) set the cache sizes for various CPUs. The CPU family descriptions in translate_init.c can set these sizes - this patch adds correct information for POWER7, I'm leaving other CPU types to people who have a physical example to verify against. In addition, for -cpu host we take the values advertised by the host (if available) and use those to override the information based on PVR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Add breakpoint registers for 603 and e300Fabien Chouteau1-0/+34
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450Fabien Chouteau1-11/+11
According to the different user's manuals, the vector offset for system reset (both /HRESET and /SRESET) is 0x00100. This patch may break support of some executables, as the power-on start address may change. For a specific board, if the power-on start address is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this should be fixed in board's initialization code. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Remove env->hreset_excp_prefixFabien Chouteau1-30/+12
This value is not needed if we use correctly the MSR[IP] bit. excp_prefix is always 0x00000000, except when the MSR[IP] bit is implemented and set to 1, in that case excp_prefix is 0xfff00000. The handling of MSR[IP] was already implemented but not used at reset because the value of env->msr was changed "manually". The patch uses the function hreg_store_msr() to set env->msr, this ensures a good handling of MSR[IP] at reset, and therefore a good value for excp_prefix. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Enable ISEL on POWER7Aurelien Jarno1-1/+1
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7. Given this is trapped and emulated by the Linux kernel, I guess it went unnoticed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use QOM method dispatch for MMU fault handlingDavid Gibson1-1/+53
After previous cleanups, the many scattered checks of env->mmu_model in the ppc MMU implementation have, at least for "classic" hash MMUs been reduced (almost) to a single switch at the top of cpu_ppc_handle_mmu_fault(). An explicit switch is still a pretty ugly way of handling this though. Now that Andreas Färber's CPU QOM cleanups for ppc have gone in, it's quite straightforward to instead make the handle_mmu_fault function a QOM method on the CPU object. This patch implements such a scheme, initializing the method pointer at the same time as the mmu_model variable. We need to keep the latter around for now, because of the MMU types (BookE, 4xx, et al) which haven't been converted to the new scheme yet, and also for a few other uses. It would be good to clean those up eventually. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash64: Implement Virtual Page Class Key ProtectionDavid Gibson1-0/+49
Version 2.06 of the Power architecture describes an additional page protection mechanism. Each virtual page has a "class" (0-31) recorded in the PTE. The AMR register contains bits which can prohibit reads and/or writes on a class by class basis. Interestingly, the AMR is userspace readable and writable, however user mode writes are masked by the contents of the UAMOR which is privileged. This patch implements this protection mechanism, along with the AMR and UAMOR SPRs. The architecture also specifies a hypervisor-privileged AMOR register which masks user and supervisor writes to the AMR and UAMOR. We leave this out for now, since we don't at present model hypervisor mode correctly in any case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix 32-bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson1-255/+0
The PowerPC 620 was the very first 64-bit PowerPC implementation, but hardly anyone ever actually used the chips. qemu notionally supports the 620, but since we don't actually have code to implement the segment table, the support is broken (quite likely in other ways too). This patch, therefore, removes all remaining pieces of 620 support, to stop it cluttering up the platforms we actually care about. This includes removing support for the ASR register, used only on segment table based machines. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22PPC/GDB: handle read and write of fpscrFabien Chouteau1-1/+1
Although the support of this register may be uncomplete, there are no reason to prevent the debugger from reading or writing it. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-0/+1
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-08target-ppc: Move CPU aliases out of translate_init.cAndreas Färber1-198/+3
Move array of CPU aliases to cpu-models.c, alongside model definitions. This requires to zero-terminate the aliases array since ARRAY_SIZE() can no longer be used in translate_init.c then. Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Report CPU aliases for QMPAndreas Färber1-0/+21
The QMP query-cpu-definitions implementation iterated over CPU classes only, which were getting less and less as aliases were extracted. Keep them in QMP as valid -cpu arguments even if not guaranteed stable. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: List alias names alongside CPU modelsAndreas Färber1-12/+11
Revert adding a separate -cpu ? output section for aliases and list them per CPU subclass. Requested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Make host CPU a subclass of the host's CPU modelAndreas Färber1-7/+8
This avoids assigning individual class fields and contributors forgetting to add field assignments in KVM-only code. ppc_cpu_class_find_by_pvr() requires the CPU model classes to be registered, so defer host CPU type registration to kvm_arch_init(). Only register the host CPU type if there is a class with matching PVR. This lets us drop error handling from instance_init. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix PPC_DUMP_SPR_ACCESS buildAndreas Färber1-2/+2
A victim of the d523dd00a7d73b28f2e99acf45a4b3f92e56e40a AREG0 conversion, insert the missing cpu_env arguments. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Add mechanism for synchronizing SPRs with KVMDavid Gibson1-49/+65
Currently when runing under KVM on ppc, we synchronize a certain number of vital SPRs to KVM through the SET_SREGS call. This leaves out quite a lot of important SPRs which are maintained in KVM. It would be helpful to have their contents in qemu for debugging purposes, and when we implement migration it will be vital, since they include important guest state that will need to be restored on the target. This patch sets up for synchronization of any registers supported by the KVM ONE_REG calls. A new variant on spr_register() allows a ONE_REG id to be stored with the SPR information. When we set/get information to KVM we also synchronize any SPRs so registered. For now we set this mechanism up to synchronize a handful of important registers that already have ONE_REG IDs, notably the DAR and DSISR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Change "POWER7" CPU aliasAndreas Färber1-1/+1
Let it resolve to v2.3 rather than v2.0. Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Split model definitions out of translate_init.cAndreas Färber1-1905/+2
Now that model definitions only reference their parent type, model definitions are independent of the family definitions and can be compiled independently of TCG translation. Keep all #if defined(TODO) code local to cpu-models.c. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Update Coding Style for CPU modelsAndreas Färber1-100/+100
Drop the space in #if defined (TODO). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Turn descriptive CPU model comments into device descriptionsAndreas Färber1-860/+754
Fix microcontroller typo while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Turn descriptive CPU family comments into device descriptionsAndreas Färber1-52/+107
This gets rid of some more overly long comments that have lost most of their purpose now that in most cases there's only two functions left per CPU family. The class field is inherited by the actual CPU models, so override it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Set remaining fields on CPU family classesAndreas Färber1-430/+375
Now POWERPC_DEF_SVR() no longer sets family-specific fields itself. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Register all types for TARGET_PPCEMBAndreas Färber1-9/+34
Don't attempt to suppress registration of CPU types, since the criteria is actually a property of the class and should thus become a field. Since we can't check a field set in a class_init function before registering the type that leads to execution of that function, guard the -cpu class lookup instead and suppress exposing these classes in -cpu ? and in QMP. In case someone tries to hot-add an incompatible CPU via device_add, error out in realize. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Set instruction flags on CPU family classesAndreas Färber1-495/+499
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Introduce abstract CPU family typesAndreas Färber1-69/+432
Instead of assigning *_<family> constants, set .parent to a family type. Introduce a POWERPC_FAMILY() macro to keep type registration close to its implementation. This macro will need tweaking later. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Convert CPU definitionsAndreas Färber1-83/+80
Turn the array of model definitions into a set of self-registering QOM types with their own class_init. Unique identifiers are obtained from the combination of PVR, SVR and family identifiers; this requires all alias #defines to be removed from the list. Possibly there are some more left after this commit that are not currently being compiled. Prepares for introducing abstract intermediate CPU types for families. Keep the right-aligned macro line breaks within 78 chars to aid three-way merges. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Get model name from type nameAndreas Färber1-3/+10
We are about to drop the redundant name field along with ppc_def_t. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract POWER7 aliasAndreas Färber1-2/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 970 aliasesAndreas Färber1-6/+2
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 405GPe aliasAndreas Färber1-3/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC8240 aliasAndreas Färber1-5/+3
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC5200/MPC5200B aliasesAndreas Färber1-10/+2
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC52xx aliasAndreas Färber1-5/+2
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
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