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2011-10-06PPC: booke timersFabien Chouteau1-0/+39
While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Gdbstub: handle read of fpscrFabien Chouteau1-2/+1
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson1-1/+22
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-3/+3
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-06-17PPC: move TLBs to their own arraysAlexander Graf1-1/+26
Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-03ppc: Fix compilation for ppc64-softmmuStefan Weil1-6/+6
When QEMU was configured with --enable-debug-tcg, compilation fails in spr_write_booke206_mmucsr0() and in spr_write_booke_pid(). Similar changes are also needed in conditional code which is normally unused. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-14Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno1-80/+202
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: Qdev'ify e500 pci PPC MPC7544DS: Use new TLB helper function PPC: Implement e500 (FSL) MMU PPC: Add another 64 bits to instruction feature mask PPC: Add GS MSR definition PPC: Make MPC8544DS emulation work w/o KVM PPC: Make MPC8544DS obey -cpu switch Fix off-by-one error in sizing pSeries hcall table ppc64: Fix out-of-tree builds kvm: ppc: warn user on PAGE_SIZE mismatch kvm: ppc: detect old headers monitor: add PPC BookE SPRs kvm: ppc: fixes for KVM_SET_SREGS on init ppc64: Don't try to build sPAPR RTAS on Darwin Place pseries vty devices at addresses more similar to existing machines Make pSeries 'model' property more closely resemble real hardware pseries: Increase maximum CPUs to 256
2011-05-12PPC: Implement e500 (FSL) MMUAlexander Graf1-49/+114
Most of the code to support e500 style MMUs is already in place, but we're missing on some of the special TLB0-TLB1 handling code and slightly different TLB modification. This patch adds support for the FSL style MMU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12PPC: Add another 64 bits to instruction feature maskAlexander Graf1-33/+90
To enable quick runtime detection of instruction groups to the currently selected CPU emulation, we have a feature mask of what exactly the respective instruction supports. This feature mask is 64 bits long and we just successfully exceeded those 64 bits. To add more features, we need to think of something. The easiest solution that came to my mind was to simply add another 64 bits that we can also match on. Since the comparison is only done on start of the qemu process to generate an internal opcode calling table, we should be fine on any performance penalties here. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-08Fix typos in comments (instanciation -> instantiation)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-04-01Add POWER7 support for ppcDavid Gibson1-0/+107
This adds emulation support for the recent POWER7 cpu to qemu. It's far from perfect - it's missing a number of POWER7 features so far, including any support for VSX or decimal floating point instructions. However, it's close enough to boot a kernel with the POWER7 PVR. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Parse SDR1 on mtspr instead of at translate timeDavid Gibson1-6/+1
On ppc machines with hash table MMUs, the special purpose register SDR1 contains both the base address of the encoded size (hashed) page tables. At present, we interpret the SDR1 value within the address translation path. But because the encodings of the size for 32-bit and 64-bit are different this makes for a confusing branch on the MMU type with a bunch of curly shifts and masks in the middle of the translate path. This patch cleans things up by moving the interpretation on SDR1 into the helper function handling the write to the register. This leaves a simple pre-sanitized base address and mask for the hash table in the CPUState structure which is easier to work with in the translation path. This makes the translation path more readable. It addresses the FIXME comment currently in the mtsdr1 helper, by validating the SDR1 value during interpretation. Finally it opens the way for emulating a pSeries-style partition where the hash table used for translation is not mapped into the guests's RAM. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement missing parts of the logic for the POWER PURRDavid Gibson1-0/+8
The PURR (Processor Utilization Resource Register) is a register found on recent POWER CPUs. The guts of implementing it at least enough to get by are already present in qemu, however some of the helper functions needed to actually wire it up are missing. This patch adds the necessary glue, so that the PURR can be wired up when we implement newer POWER CPU targets which include it. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-02-16Handle icount for powerpc tbl/tbu/decr load and store.Tristan Gingold1-0/+42
Handle option '-icount X' on powerpc targets. Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-1/+1
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-30powerpc: Add a ppc-440x5 Xilinx modelEdgar E. Iglesias1-2/+4
Add a powerpc 440x5 with the model ID on the Xilinx virtex5. Connect the 440x5 to the 40x interrupt logic. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2010-07-19target-ppc: fix power mode checking on 7400/7410Aurelien Jarno1-2/+2
Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC 7400 and 7410 support it.
2010-03-26target-ppc: generic PowerPC TBLDmitry Ilyevsky1-4/+4
Time base SPRs TBL/TBU should be accessible in user/priv modes for reading as specified in POWER ISA documentation. Therefore SPRs permissions were changed in gen_tbl function. Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: simpler definitions for microcontrollers based on e300Thomas Monjalon1-68/+44
No need to alias e300 core for each CPU package. Differences between microcontrollers have to be implemented in a higher layer than translate_init.c Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: add declarations of microcontrollers based on e300Thomas Monjalon1-8/+40
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: better support of e300 CPU coreThomas Monjalon1-2/+8
Declare HID2 register. Use high BATs for e300 (8 instead of 4). Fix index of high BATs registers. Before the fix, IBAT4-7 were overwriting IBAT0-3. Signed-off-by: François Armand <francois.armand@os4i.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-39/+39
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-39/+39
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-16Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plxBlue Swirl1-2/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela1-2/+2
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-13target-ppc: enable PPC_MFTB for 44xBaojun Wang1-6/+6
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a preserved instruction: PPC440_UM2013.pdf, p.445, table A-3 when I compile a kernel (2.6.30, bamboo_defconfig/440EP & canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump vmlinux I have also checked the ppc 440x[456], 460S, 464, they also should support mftb. The following patch enable mftb for all ppc 440 variants, including: 440EP, 440GP, 440x4, 440x5 and 460 Signed-off-by: Baojun Wang <wangbj@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-06-23target-ppc: permit linux-user to read PVRNathan Froyd1-1/+7
Access to the PVR SPR is normally forbidden from userspace apps. The Linux kernel, however, fixes up reads in the appropriate trap handler. To permit applications that read PVR to run on QEMU, then, we need to implement the same handling of PVR reads. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-06-17Replace ELF section hack with normal tableBlue Swirl1-9/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-16target-ppc: expose cpu capability flagsNathan Froyd1-0/+1
Do this so other pieces of code can make decisions based on the capabilities of the CPU we're emulating. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-04-28Fix powerpc 604 reset vectorTristan Gingold1-2/+2
According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is set for hreset and the vector is at offset 0x100 from the exception prefix. No difference in this area between 604 and 604e. Signed-off-by: Tristan Gingold <gingold@adacore.com>
2009-04-28Fix PPC resetBlue Swirl1-20/+23
2009-03-10target-ppc: fix commit r6789aurel321-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09target-ppc: free a tcg temp variableaurel321-0/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09target-ppc: add support for reading/writing spefscraurel321-8/+23
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix off-by-one errors for Altivec and SPE registersaurel321-8/+8
Altivec and SPE both have 34 registers in their register sets, not 35 with a missing register 32. GDB would ask for register 32 of the Altivec (resp. SPE) registers and the code would claim it had zero width. The QEMU GDB stub code would then return an E14 to GDB, which would complain about not being sure whether p packets were supported or not. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Keep SLB in-CPUblueswir11-1/+1
Real 970 CPUs have the SLB not memory backed, but inside the CPU. This breaks bridge mode for 970 for now, but at least keeps us from overwriting physical addresses 0x0 - 0x300, rendering our interrupt handlers useless. I put in a stub for bridge mode operation that could be enabled easily, but for now it's safer to leave that off I guess (970fx doesn't have bridge mode AFAIK). Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6757 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Nop some SPRs on 970fxblueswir11-0/+12
Linux tries to access some SPRs on PPC64 boot. Let's just ignore those for the 970fx for now to make it happy. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-03target-ppc: improve mfcr/mtcrfaurel321-1/+0
- use ctz32 instead of ffs - 1 - small optimisation of mtcrf - add the name of both opcodes Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02kvm/powerpc: Add irq support for E500 coreaurel321-2/+3
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28Implement HIORblueswir11-8/+21
A real 970 CPU starts up with HIOR=0xfff00000 and triggers a reset exception, basically ending up at IP 0xfff001000. Later on this HIOR has to be set to 0 by the firmware in order to enable the OS to handle interrupts on its own. This patch maps HIOR to exec_prefix, which does the same thing internally in qemu already. It replaces the previous patch that changed the 970 initialization constants, as this is the clean solution to the same problem. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6656 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09target-ppc: Model e500v{1,2} CPUs more accuratelyaurel321-102/+125
The e500v1 chips only have single-precision floating point; don't say we support the double-precision floating-point instructions on such chips. Also add an e500v1 -cpu argument for a generic e500v1. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6576 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-09target-ppc: Model SPE floating-point instructions more accuratelyaurel321-9/+9
Single-precision and double-precision floating-point instructions should be separated into their own categories, since some chips only support single-precision instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-2/+0
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-03Add calls to initialize VSCR on appropriate machinesaurel321-0/+22
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6507 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add SPE register read/write using XMLaurel321-0/+50
Don't read/write SPEFSCR until we figure out what to do about exceptions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6425 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add Altivec register read/write using XMLaurel321-0/+50
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6424 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add float register read/write using XMLaurel321-0/+32
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Include gdbstub.haurel321-0/+1
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6422 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
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