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2012-10-06Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agrafAurelien Jarno6-146/+152
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (35 commits) PPC: KVM: Fix BAT put PPC: e500: Only expose even TLB sizes in initial TLB ppc/pseries: Reset VPA registration on CPU reset pseries: Don't test for MSR_PR for hypercalls under KVM PPC: e500: calculate initrd_base like dt_base PPC: e500: increase DTC_LOAD_PAD device tree: simplify dumpdtb code fdt: move dumpdtb interpretation code to device_tree.c target-ppc: Remove unused power_mode field from cpu state pseries: Set hash table size based on RAM size pseries: Remove unnecessary locking from PAPR hash table hcalls ppc405_uc: Fix buffer overflow target-ppc: KVM: Fix some kernel version edge cases for kvmppc_reset_htab() pseries: Fix semantics of RTAS int-on, int-off and set-xive functions pseries: Rework implementation of TCE bypass pseries: Remove never used flags field from spapr vio devices pseries: Remove XICS irq type enum type pseries: Remove C bitfields from xics code pseries: Small cleanup to H_CEDE implementation pseries: Fix XICS reset ...
2012-10-05ppc: avoid buffer overrun: use pstrcpy, not strncpyJim Meyering1-1/+1
A terminal NUL is required by caller's use of strchr. It's better not to use strncpy at all, since there is no need to zero out hundreds of trailing bytes for each iteration. Signed-off-by: Jim Meyering <meyering@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-05PPC: KVM: Fix BAT putAlexander Graf1-4/+5
In the sregs API, upper and lower 32bit segments of the BAT registers are swapped when doing a set. Since we need to support old kernels out there, don't bother to fix it in the kernel, but instead work around the problem in QEMU by swapping on put. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04Make target_phys_addr_t 64 bits unconditionallyAvi Kivity1-3/+1
The hassle and compile time overhead of maintaining both 32-bit and 64-bit capable source isn't worth the tiny performance advantage which is seen on a minority of configurations. Switch to compiling libhw only once, with target_phys_addr_t unconditionally typedefed to uint64_t. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-05ppc/pseries: Reset VPA registration on CPU resetDavid Gibson1-0/+8
The ppc specific CPU state contains several variables which track the VPA, SLB shadow and dispatch trace log. These are structures shared between OS and hypervisor that are used on the pseries machine to track various per-CPU quantities. The address of these structures needs to be registered by the guest on each boot, however currently this registration is not cleared when we reset the cpu. This patch corrects this bug. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04target-ppc: Remove unused power_mode field from cpu stateDavid Gibson2-3/+2
CPUPPCState includes a variable 'power_mode' which is used nowhere. This patch removes it. This includes saving a dummy zero in its place during vmsave, to avoid breaking the save format. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04target-ppc: KVM: Fix some kernel version edge cases for kvmppc_reset_htab()David Gibson1-5/+25
The kvmppc_reset_htab() function invokes the KVM_PPC_ALLOCATE_HTAB vm ioctl to request KVM to allocate and reset a hash page table for the guest - it returns the size of hash table allocated, or 0 to indicate that qemu needs to allocate the hash table itself. In practice qemu needs to allocate the htab for full emulation and with Book3sPR KVM, but the kernel has to allocate it for Book3sHV KVM (the hash table needs to be physically contiguous in that case). Unfortunately, the logic in this function is incorrect for some existing kernels. Specifically: * at least some PR KVM versions advertise the relevant capability but don't actually implement the ioctl(), returning ENOTTY. * For old kernels which don't have the capability, we currently return 0. This is correct for PV KVM, where we need to allocate the htab, but not for HV KVM - kernels of this era always allocate a 16MB hash table per guest. This patch corrects both of these edge cases. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04pseries: Add support for new KVM hash table control callDavid Gibson2-0/+48
This adds support for then new "reset htab" ioctl which allows qemu to properly cleanup the MMU hash table when the guest is reset. With the corresponding kernel support, reset of a guest now works properly. This also paves the way for indicating a different size hash table to the kernel and for the kernel to be able to impose limits on the requested size. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04ppc: Make kvm_arch_put_registers() put *all* the registersDavid Gibson1-39/+50
At least when invoked with high enough 'level' arguments, kvm_arch_put_registers() is supposed to copy essentially all the cpu state as encoded in qemu's internal structures into the kvm state. Currently the ppc version does not do this - it never calls KVM_SET_SREGS, for example, and therefore never sets the SDR1 and various other important though rarely changed registers. Instead, the code paths which need to set these registers need to explicitly make (conditional) kvm calls which transfer the changes to kvm. This breaks the usual model of handling state updates in qemu, where code just changes the internal model and has it flushed out to kvm automatically at some later point. This patch fixes this for Book S ppc CPUs by adding a suitable call to KVM_SET_SREGS and als to KVM_SET_ONE_REG to set the HIOR (the only register that is set with that call so far). This lets us remove the hacks to explicitly set these registers from the kvmppc_set_papr() function. The problem still exists for Book E CPUs (which use a different version of the kvm_sregs structure). But fixing that has some complications of its own so can be left to another day. Lkewise, there is still some ugly code for setting the PVR through special calls to SET_SREGS which is left in for now. The PVR needs to be set especially early because it can affect what other features are available on the CPU, so I need to do more thinking to see if it can be integrated into the normal paths or not. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04target-ppc: get rid of the HANDLE_NAN{1, 2, 3} macrosAurelien Jarno1-21/+0
We can finally get rid of the ugly HANDLE_NAN{1,2,3} macros. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04target-ppc: use the softfloat float32_muladd functionAurelien Jarno1-43/+14
Use the new softfloat float32_muladd() function to implement the vmaddfp and vnmsubfp instructions. As a bonus we can get rid of the call to the HANDLE_NAN3 macro, as the NaN handling is directly done at the softfloat level. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04target-ppc: use the softfloat min/max functionsAurelien Jarno1-21/+2
Use the new softfloat float32_min() and float32_max() to implement the vminfp and vmaxfp instructions. As a bonus we can get rid of the call to the HANDLE_NAN2 macro, as the NaN handling is directly done at the softfloat level. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-10-04target-ppc: simplify NaN propagation for vector functionsAurelien Jarno1-19/+7
Commit e024e881bb1a8b5085026589360d26ed97acdd64 provided a pickNaN() function for PowerPC, implementing the correct NaN propagation rules. Therefore there is no need to test the operands manually, we can rely on the softfloat code to do that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-28target-ppc: fix altivec instructionsAurelien Jarno1-1/+1
Altivec instructions are not working anymore in PowerPC emulation, following commit d15f74fb, which inverted two registers in the call to helper. Fix that. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-15Merge remote-tracking branch 'agraf/ppc-for-upstream' into stagingAnthony Liguori1-1/+1
* agraf/ppc-for-upstream: (24 commits) openpic: Added BRR1 register pseries: Update SLOF firmware image pseries dma: DMA window params added to PHB and DT population changed pseries: Add PCI MSI/MSI-X support pseries: Add trace event for PCI irqs pseries: Export find_phb() utility function for PCI code pseries: added allocator for a block of IRQs pseries: Separate PCI RTAS setup from common from emulation specific PCI setup pseries: Rework irq assignment to avoid carrying qemu_irqs around pseries: Remove extraneous prints pseries: Update SLOF PPC: spapr: Remove global variable PPC: spapr: Rework VGA select logic xbzrle: fix compilation on ppc32 spapr: Add support for -vga option Add one new file vga-pci.h and cleanup on all platforms Revert "PPC: e500: Use new MPIC dt format" ppc: Fix bug in handling of PAPR hypercall exits PPC: e500: add generic e500 platform PPC: e500: split mpc8544ds machine from generic e500 code ...
2012-08-15win32: provide separate macros for weak decls and definitionsAnthony Liguori1-2/+2
mingw32 seems to want the declaration to also carry the weak attribute. Strangely, gcc on Linux absolutely does not want the declaration to be marked as weak. This may not be the right fix, but it seems to do the trick. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-08-15ppc: Fix bug in handling of PAPR hypercall exitsDavid Gibson1-1/+1
Currently for powerpc, kvm_arch_handle_exit() always returns 1, meaning that its caller - kvm_cpu_exec() - will always exit immediately afterwards to the loop in qemu_kvm_cpu_thread_fn(). There's no need to do this. Once we've handled the hypercall there's no reason we can't go straight around and KVM_RUN again, which is what ret = 0 will signal. The only exception might be for hypercalls which affect the state of cpu_can_run(), however the only one that might do this is H_CEDE and for kvm that is always handled in the kernel, not qemu. Furtherm setting ret = 0 means that when exit_requested is set from a hypercall, we will enter KVM_RUN once more with a signal which lets the the kernel do its internal logic to complete the hypercall with out actually executing any more guest code. This is important if our hypercall also triggered a reset, which previously would re-initialize everything without completing the hypercall. This caused the kernel to get confused because it thought the guest was still in the middle of a hypercall when it has actually been reset. This patch therefore changes to ret = 0, which is both a bugfix and a small optimization. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-08-13target-ppc: add implementation of query-cpu-definitions (v2)Anthony Liguori1-0/+26
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2012-06-27pseries: Convert sPAPR TCEs to use generic IOMMU infrastructureDavid Gibson1-2/+2
The pseries platform already contains an IOMMU implementation, since it is essential for the platform's paravirtualized VIO devices. This IOMMU support is currently built into the implementation of the VIO "bus" and the various VIO devices. This patch converts this code to make use of the new common IOMMU infrastructure. We don't yet handle synchronization of map/unmap callbacks vs. invalidations, this will require some complex interaction with the kernel and is not a major concern at this stage. Cc: Alex Graf <agraf@suse.de> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-24target-ppc: Fix 2nd parameter for tcg_gen_shri_tlStefan Weil1-1/+1
This fixes a compiler error when QEMU was configured with --enable-debug. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24target-ppc: Fix build with --enable-debugStefan Weil1-1/+1
The order of the arguments was wrong (copy+paste error). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE206: Bump MAS2 to 64bitAlexander Graf1-1/+1
On 64bit capable systems, MAS2 can actually hold a 64bit virtual page address. So increase the mask for its EPN. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Support 32 and 64 bit wide MAS2Alexander Graf1-1/+18
The MAS registers on BookE are all 32 bit wide, except for MAS2, which can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR setting code, so that the guest can never write invalid values in them. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Extract SPR dump generation into its own functionAlexander Graf1-12/+18
This patch moves the debug #ifdef'ed SPR trace generation into its own function, so we can call it from multiple places. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add e5500 CPU targetAlexander Graf1-3/+93
This patch adds e5500's CPU initialization to the TCG CPU initialization code. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Make ivpr selectable by CPU typeAlexander Graf1-4/+5
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let the CPU initialization function pass in its mask itself, so we can easily extend it. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Implement EPR SPRAlexander Graf4-0/+38
On the e500 series, accessing SPR_EPR magically turns into an access at that CPU's IACK register on the MPIC. Implement that logic to get kernels that make use of that feature work. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add support for MSR_CMAlexander Graf4-6/+16
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to support running 64bit code with MSR_CM set. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add some booke SPR definesAlexander Graf1-0/+22
The number of SPRs avaiable in different PowerPC chip is still increasing. Add definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc64: Rudimentary Support for extra page sizes on server CPUsBenjamin Herrenschmidt5-0/+272
More recent Power server chips (i.e. based on the 64 bit hash MMU) support more than just the traditional 4k and 16M page sizes. This can get quite complicated, because which page sizes are supported, which combinations are supported within an MMU segment and how these page sizes are encoded both in the SLB entry and the hash PTE can vary depending on the CPU model (they are not specified by the architecture). In addition the firmware or hypervisor may not permit use of certain page sizes, for various reasons. Whether various page sizes are supported on KVM, for example, depends on whether the PR or HV variant of KVM is in use, and on the page size of the memory backing the guest's RAM. This patch adds information to the CPUState and cpu defs to describe the supported page sizes and encodings. Since TCG does not yet support any extended page sizes, we just set this to NULL in the static CPU definitions, expanding this to the default 4k and 16M page sizes when we initialize the cpu state. When using KVM, however, we instead determine available page sizes using the new KVM_PPC_GET_SMMU_INFO call. For old kernels without that call, we use some defaults, with some guesswork which should do the right thing for existing HV and PR implementations. The fallback might not be correct for future versions, but that's ok, because they'll have KVM_PPC_GET_SMMU_INFO. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24booke_206_tlbwe: Discard invalid bits in MAS2Fabien Chouteau1-2/+15
The size of EPN field in MAS2 depends on page size. This patch adds a mask to discard invalid bits in EPN field. Definition of EPN field from e500v2 RM: EPN Effective page number: Depending on page size, only the bits associated with a page boundary are valid. Bits that represent offsets within a page are ignored and should be cleared. There is a similar (but more complicated) definition in PowerISA V2.06. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Make hbrev table constBlue Swirl1-1/+1
Lookup table 'hbrev' is never written to, so add a 'const' qualifier. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Add missing breakBlue Swirl1-0/+1
Add obviously missing 'break' statement. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Move load and store helpers, switch to AREG0 free modeBlue Swirl5-89/+90
Add an explicit CPUPPCState parameter instead of relying on AREG0 and rename op_helper.c (which only contains load and store helpers) to mem_helper.c. Remove AREG0 swapping in tlb_fill(). Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation and interrupt handling, cpu_{ld,st}{l,uw}_data in loads and stores. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Move misc helpers from helper.c to misc_helper.cBlue Swirl2-9/+9
Move more misc helpers from helper.c to misc_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Avoid AREG0 for misc helpersBlue Swirl5-27/+25
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Split off misc helpersBlue Swirl3-94/+118
Move misc helpers from op_helper.c to misc_helpers.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Avoid AREG0 for timebase helpersBlue Swirl5-69/+71
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Split off timebase helpersBlue Swirl3-135/+162
Move decrementer and timebase helpers to a dedicated file. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Cleanup MMU mergeBlue Swirl2-106/+35
Remove useless wrappers. In some cases 'int' parameters are changed to uint32_t. Make internal functions static. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> [agraf: fix kvm compilation] Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Move MMU helpers from helper.c to mmu_helper.cBlue Swirl2-2475/+2471
Move more MMU helpers from helper.c to mmu_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> [update to current helper.c state] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Avoid a warning with the next patchBlue Swirl1-2/+2
When the code is moved together by the next patch, compiler detects a possible uninitialized variable use. Avoid the warning by initializing the variables. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Avoid AREG0 for MMU etc. helpersBlue Swirl5-133/+142
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Split MMU etc. helpers from op_helper.cBlue Swirl3-854/+884
Move MMU, TLB, SLB and BAT ops to mmu_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Avoid AREG0 for integer and vector helpersBlue Swirl4-191/+280
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> [fix unwanted whitespace line in Makefile.target] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Split integer and vector opsBlue Swirl3-1500/+1540
Move integer and vector ops to int_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Avoid AREG0 for FPU and SPE helpersBlue Swirl4-322/+346
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Split FPU and SPE opsBlue Swirl3-1710/+1733
Move FPU and SPE helpers from op_helper.c to fpu_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24ppc: Move exception helpers from helper.c to excp_helper.cBlue Swirl3-746/+745
Move exception helpers from helper.c to excp_helper.c and make cpu_dump_rfi() static. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
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