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2013-05-18remove some double-includesMichael Tokarev1-2/+0
Some source files #include the same header more than once for no good reason. Remove second #includes in such cases. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-08PPC: Depend behavior of cmp instructions only on instruction encodingAlexander Graf1-16/+16
When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, it still behaves identical to what it does when SF is on. Remove the implicit difference in the code. Also, on most 32bit CPUs we should always treat the compare as 32bit compare, as the CPU will ignore the L bit. This is not true for e500mc, but that's up for a different patch. Reported-by: Torbjorn Granlund <tg@gmplib.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-08PPC: Fix rldclAlexander Graf1-2/+0
The implementation for rldcl tried to always fetch its parameters from the opcode, even though the opcode was already passed in in decoded and different forms. Use the parameters instead, fixing rldcl. Reported-by: Torbjorn Granlund <tg@gmplib.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06target-ppc: Add read and write of PPR SPRAnton Blanchard1-0/+4
Recent Linux kernels save and restore the PPR across exceptions so we need to handle it. Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06target-ppc: Fix invalid SPR read/write warningsAnton Blanchard1-16/+16
Invalid and privileged SPR warnings currently print the wrong address. While fixing that, also make it clear that we are printing both the decimal and hexadecimal SPR number. Before: Trying to read invalid spr 896 380 at 0000000000000714 After: Trying to read invalid spr 896 (0x380) at 0000000000000710 Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06PPC: Add MMU type for 2.06 with AMR but no TB pagesAlexander Graf2-0/+7
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB MMU capability from the MMU type mask, but not the AMR bit. This leads to us having a new MMU type that we don't check for in our MMU management functions. Add the new type, so that we don't have to worry about breakage there. We're not going to use the TCG MMU management in that case anyway. The long term fix for this will be to move all these MMU management functions to class callbacks. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-27target-ppc: slightly optimize lfiwaxAurelien Jarno1-4/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-26target-ppc: add support for extended mtfsf/mtfsfi formsAurelien Jarno2-22/+41
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new W field to select the upper part of the FPCSR register. For that the helper is changed to handle 64-bit input values and mask with up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit marked as invalid anymore. Instead this is checked in the helper, which therefore needs to access to the insns/insns_flags2. They are added in the DisasContext struct. Finally change all accesses to the opcode fields through extract helpers, prefixed with FP for consistency. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate store doubleword pair instructionsAurelien Jarno1-0/+48
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate load doubleword pair instructionsAurelien Jarno1-0/+48
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate lfiwax instructionAurelien Jarno1-0/+21
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: fix tcg debug error] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate fcpsgn instructionAurelien Jarno1-0/+14
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate prtyw and prtyd instructionsAurelien Jarno1-0/+34
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: fix 32-bit host compile, simplify code] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate cmpb instructionAurelien Jarno3-0/+24
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: add instruction flags for Book I 2.05Aurelien Jarno2-2/+4
.. and enable it on POWER7 CPU. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: optimize fabs, fnabs, fnegAurelien Jarno3-40/+34
fabs, fnabs and fneg are just flipping the bit sign of an FP register, this can be implemented in TCG instead of using softfloat. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Fix dcbz for linux-user on 970Alexander Graf1-1/+1
The default with linux-user for dcbz on 970 is to emulate 32 byte clears. However, redoing the dcbzl support we added a check to not honor the bit in HID5 that sets this. Remove the #ifdef check on linux user, so that we get 32 byte clears again. Reported-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26powerpc: correctly handle fpu exceptions.Tristan Gingold1-11/+12
Raise the exception on the first occurence, do not wait for the next floating point operation. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Synchronize VPA state with KVMDavid Gibson1-0/+120
For PAPR guests, KVM tracks the various areas registered with the H_REGISTER_VPA hypercall. For full emulation, of course, these are tracked within qemu. At present these values are not synchronized. This is a problem for reset (qemu's reset of the VPA address is not pushed to KVM) and will also be a problem for savevm / migration. The kernel now supports accessing the VPA state via the ONE_REG interface, this patch adds code to qemu to use that interface to keep the qemu and KVM ideas of the VPA state synchronized. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Add more stubs for POWER7 PMU registersDavid Gibson2-0/+13
In addition to the performance monitor registers found on nearly all 6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an extra control register (MMCRA). This patch adds stub support for them to qemu - the registers won't do anything, but with this change won't cause illegal instruction traps accessing them. They're also registered with their ONE_REG ids, so their value will be kept in sync with KVM where appropriate. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26pseries: Fixes and enhancements to L1 cache propertiesDavid Gibson3-0/+14
PAPR requires that the device tree's CPU nodes have several properties with information about the L1 cache. We already create two of these properties, but with incorrect names - "[id]cache-block-size" instead of "[id]-cache-block-size" (note the extra hyphen). We were also missing some of the required cache properties. This patch adds the [id]-cache-line-size properties (which have the same values as the block size properties in all current cases). We also add the [id]-cache-size properties. Adding the cache sizes requires some extra infrastructure in the general target-ppc code to (optionally) set the cache sizes for various CPUs. The CPU family descriptions in translate_init.c can set these sizes - this patch adds correct information for POWER7, I'm leaving other CPU types to people who have a physical example to verify against. In addition, for -cpu host we take the values advertised by the host (if available) and use those to override the information based on PVR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26pseries: Fix incorrect calculation of RMA size in certain configurationsDavid Gibson1-1/+25
For the pseries machine, we need to advertise to the guest the size of its RMA - that is the amount of memory it can access with the MMU off. For HV KVM, this is constrained by the hardware limitations on the virtual RMA of one hash PTE per PTE group in the hash page table. We already had code to calculate this, but it was assuming the VRMA page size was the same as the (host) backing page size for guest RAM. In the case of a host kernel configured for 64k base page size, but running on hardware (or firmware) which only allows 4k pages, the hose will do all its allocations with a 64k page size, but still use 4k hardware pages for actual mappings. Usually that's transparent to things running under the host, but in the case of the maximum VRMA size it's not. This patch refines the RMA size calculation to instead use the largest available hardware page size (as reported by the SMMU_INFO call) which is less than or equal to the backing page size. This now gives the correct RMA size in all cases I've tested. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26Enable kvm emulated watchdogBharat Bhushan2-0/+98
Enable the KVM emulated watchdog if KVM supports (use the capability enablement in watchdog handler). Also watchdog exit (KVM_EXIT_WATCHDOG) handling is added. Watchdog state machine is cleared whenever VM state changes to running. This is to handle the cases like return from debug halt etc. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: rebase to current code base, fix non-kvm cases] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Fix narrow-mode add/sub carry outputRichard Henderson1-13/+22
Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need to produce the full 64-bit addition. Simplify the conditions at the top of the functions for when we need a new temporary. Only plain addition is important enough to warrent avoiding the temporary, and the extra tcg move op that would come with it. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Add breakpoint registers for 603 and e300Fabien Chouteau1-0/+34
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450Fabien Chouteau1-11/+11
According to the different user's manuals, the vector offset for system reset (both /HRESET and /SRESET) is 0x00100. This patch may break support of some executables, as the power-on start address may change. For a specific board, if the power-on start address is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this should be fixed in board's initialization code. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: fix nego and subf*o instructionsAurelien Jarno1-1/+1
The overflow computation of nego and subf*o instructions has been broken in commit ffe30937. Contrary to other targets, the instruction is subtract from an not subtract on PowerPC. This patch fixes the issue by using the correct argument in the xor computation. Thanks to Peter Maydell for the hint. With this change the PPC emulation passes the Gwenole Beauchesne testsuite again. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Remove env->hreset_excp_prefixFabien Chouteau3-33/+12
This value is not needed if we use correctly the MSR[IP] bit. excp_prefix is always 0x00000000, except when the MSR[IP] bit is implemented and set to 1, in that case excp_prefix is 0xfff00000. The handling of MSR[IP] was already implemented but not used at reset because the value of env->msr was changed "manually". The patch uses the function hreg_store_msr() to set env->msr, this ensures a good handling of MSR[IP] at reset, and therefore a good value for excp_prefix. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: e500: advertise 4.2 MPIC only if KVM supports EPRStuart Yoder2-0/+13
Older KVM versions don't support EPR which breaks guests when we announce MPIC variants that support EPR. Catch that case and expose only MPIC version 2.0 which tells the guest that we don't support the EPR capability yet. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> [agraf: Add comment, route cap check through kvm_ppc.c] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Enable ISEL on POWER7Aurelien Jarno1-1/+1
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7. Given this is trapped and emulated by the Linux kernel, I guess it went unnoticed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-15memory: move core typedefs to qemu/typedefs.hPaolo Bonzini1-2/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move headers to include/Paolo Bonzini1-3/+3
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-22target-ppc: Use NARROW_MODE macro for tlbieRichard Henderson1-4/+3
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use NARROW_MODE macro for addressesRichard Henderson1-33/+18
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use NARROW_MODE macro for comparisonsRichard Henderson1-25/+16
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use NARROW_MODE macro for branchesRichard Henderson1-38/+24
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Fix add and subf carry generation in narrow modeRichard Henderson1-16/+48
The set of computations used in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a are only valid if the current word size == target_long size. This failed to take ppc64 in 32-bit (narrow) mode into account. Add a NARROW_MODE macro to avoid conditional compilation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use QOM method dispatch for MMU fault handlingDavid Gibson3-18/+64
After previous cleanups, the many scattered checks of env->mmu_model in the ppc MMU implementation have, at least for "classic" hash MMUs been reduced (almost) to a single switch at the top of cpu_ppc_handle_mmu_fault(). An explicit switch is still a pretty ugly way of handling this though. Now that Andreas Färber's CPU QOM cleanups for ppc have gone in, it's quite straightforward to instead make the handle_mmu_fault function a QOM method on the CPU object. This patch implements such a scheme, initializing the method pointer at the same time as the mmu_model variable. We need to keep the latter around for now, because of the MMU types (BookE, 4xx, et al) which haven't been converted to the new scheme yet, and also for a few other uses. It would be good to clean those up eventually. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Move ppc tlb_fill implementation into mmu_helper.cDavid Gibson3-42/+38
For softmmu builds the interface from the generic code to the target specific MMU implementation is through the tlb_fill() function. For ppc this is currently in mem_helper.c, whereas it would make more sense in mmu_helper.c. This patch moves it, which also allows cpu_ppc_handle_mmu_fault() to become a local function in mmu_helper.c Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Split user only code out of mmu_helper.cDavid Gibson4-31/+50
mmu_helper.c is, for obvious reasons, almost entirely concerned with softmmu builds of qemu. However, it does contain one stub function which is used when CONFIG_USER_ONLY=y - the user only versoin of cpu_ppc_handle_mmu_fault, which always triggers an exception. The entire rest of the file is surrounded by #if !defined(CONFIG_USER_ONLY). We clean this up by moving the user only stub into its own new file, removing the ifdefs and building mmu_helper.c only when CONFIG_SOFTMMU is set. This also lets us remove the #define of cpu_handle_mmu_fault to cpu_ppc_handle_mmu_fault - that name is only used from generic code for user only - so we just name our split user version by the generic name. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash64: Implement Virtual Page Class Key ProtectionDavid Gibson4-7/+98
Version 2.06 of the Power architecture describes an additional page protection mechanism. Each virtual page has a "class" (0-31) recorded in the PTE. The AMR register contains bits which can prohibit reads and/or writes on a class by class basis. Interestingly, the AMR is userspace readable and writable, however user mode writes are masked by the contents of the UAMOR which is privileged. This patch implements this protection mechanism, along with the AMR and UAMOR SPRs. The architecture also specifies a hypervisor-privileged AMOR register which masks user and supervisor writes to the AMR and UAMOR. We leave this out for now, since we don't at present model hypervisor mode correctly in any case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix 32-bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Merge translate and fault handling functionsDavid Gibson2-233/+167
ppc_hash{32,64}_handle_mmu_fault() is now the only caller of ppc_hash{32,64{_translate(), so this patch combines them together. This means that instead of one returning a variety of non-obvious error codes which then get translated into the various mmu exception conditions, we can just generate the exceptions as we discover problems in the translation path. This also removes the last usage of mmu_ctx_hash{32,64}. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for ↵David Gibson2-10/+43
get_phys_page_debug() Currently the hash mmu versionsof get_phys_page_debug() use the same ppc64_hash64_translate() function to do the translation logic as the normal mm fault handler code. That sounds like a good idea, but has some complications. The debug path doesn't need, or even want some parts of the full translation path, like permissions checking. Furthermore, the pte flags update included in the normal path means that the debug call is not quite side effect free. This patch, therefore, reimplements get_phys_page_debug as the minimal required subset of the full translation path. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>`z Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Correctly mask RPN from hash PTEDavid Gibson2-2/+2
BEHAVIOUR CHANGE At present we take the whole of word 1 of the hash PTE as the real page number used to calculate the translated address. This is incorrect, because it leaves the flags from the low bits of PTE word 1 in place in the rpm. We mostly get away with that because the value is later masked by TARGET_PAGE_MASK. More recent 64-bit CPUs also have a small number of flag bits (PP0 and KEY) in the top bits of PTE word 1. Any guest which used those bits would fail with the current code. This patch fixes the problem by correctly masking out the RPN field of PTE word 1. This is safe, even for older CPUs which didn't have PP0 and KEY, because although the RPN notionally extended to the very top of PTE word 1, none of those CPUs actually implemented that many real address bits. We add analogous masking to the 32-bit code, even though it also doesn't have the high flag bits, for consistency and clarity. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Clean up real address calculationDavid Gibson2-13/+27
More recent 64-bit hash MMUs support multiple page sizes, and PTEs for large pages only include the offset of the whole large page. But the qemu tlb only handles pages of the base size (4k) so we need to break up the large pages into 4k pieces for the qemu tlb. To do that we have a somewhat awkward piece of code that adds the folds address bits 4k and the page size from the virtual address into the real address from the pte. This patch simplifies this redefining the raddr output of ppc_hash64_translate() to be the full real address of the faulting address, rather than just the (4k) page offset. Computing that turns out to be simpler, and is fine for the caller, since it already masks with TARGET_PAGE_MASK before inserting into the qemu tlb. The multiple page size complication doesn't exist for 32-bit hash mmus, but we make an analogous cleanup there for consistency. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Clean up PTE flags updateDavid Gibson2-54/+24
Currently the ppc_hash{32,64}_pte_update_flags() helper functions update a PTE's referenced and changed bits as necessary to reflect the access. It is somewhat long winded, though. This patch open codes them in their (single) callers, in a simpler way. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash64: Factor SLB N bit into permissions bitsDavid Gibson1-1/+2
BEHAVIOUR CHANGE Currently, for 64-bit hash mmu, the execute protection bit placed into the qemu tlb is based only on the N (No execute) bit from the PTE. However, No Execute can also be set at the segment level. We do check this on execute faults, but this still means we could incorrectly allow execution of code from a No Execute segment, if a prior read or write fault caused the page to be loaded into the qemu tlb with PROT_EXEC set. To correct this, we (re-)check the segment level no execute permission when generating the protection bits for the qemu tlb. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Clean up permission checkingDavid Gibson2-116/+72
Currently checking of PTE permission bits is split messily amongst ppc_hash{32,64}_pp_check(), ppc_hash{32,64}_check_prot() and their callers. This patch cleans this up to have the new function ppc_hash{32,64}_pte_prot() compute the page permissions from the SLBE (for 64-bit) or segment register (32-bit) and the pte. A greatly simplified version of the actual permissions check is then open coded in the callers. The 32-bit version of ppc_hash32_pte_prot() is implemented in terms of ppc_hash32_pp_prot(), a renamed and slightly cleaned up version of the old ppc_hash32_pp_check(), which is also used for checking BAT permissions on the 601. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash32: Remove nx from context structureDavid Gibson1-4/+4
Previous cleanups have meant the nx field of the mmu_ctx_hash32 structure is now only used within ppc_hash32_translate(), and so it can be replaced by a local variable. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Don't update PTE flags when permission is deniedDavid Gibson2-10/+14
BEHAVIOUR CHANGE Currently if ppc_hash{32,64}_translate() finds a PTE matching the given virtual address, it will always update the PTE's R & C (Referenced and Changed) bits. This happens even if the PTE's permissions mean we are about to deny the translation. This is clearly a bug, although we get away with it because: a) It will only incorrectly set, never reset the bits, which should not cause guest correctness problems. b) Linux guests never use the R & C bits anyway. This patch fixes the behaviour, only updating R & C when access is granted by the PTE. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>