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2013-10-25spapr: Use DeviceClass::fw_name for device tree CPU nodeAndreas Färber1-0/+2
Instead of relying on cpu_model, obtain the device tree node label per CPU. Use DeviceClass::fw_name as source. Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN". As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name, obsoleting sPAPREnvironment::cpu_model, and spapr_create_fdt_skel() can drop its cpu_model argument. Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Fill in OpenFirmware names for some PowerPCCPU familiesAndreas Färber1-0/+3
Set the expected values for POWER7, POWER7+, POWER8 and POWER5+. Note that POWER5+ and POWER7+ are intentionally lacking the '+', so the lack of a POWER7P family constitutes no problem. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: dump-guest-memory supportAneesh Kumar K.V4-2/+262
This patch add support for dumping guest memory using dump-guest-memory monitor command. Before patch: (qemu) dump-guest-memory testcrash this feature or command is not currently supported (qemu) After patch: (qemu) dump-guest-memory testcrash (qemu) crash was able to read the file crash> bt PID: 0 TASK: c000000000c0d0d0 CPU: 0 COMMAND: "swapper/0" R0: 0000000028000084 R1: c000000000cafa50 R2: c000000000cb05b0 R3: 0000000000000000 R4: c000000000bc4cb0 R5: 0000000000000000 R6: 001efe93b8000000 R7: 0000000000000000 R8: 0000000000000000 R9: b000000000001032 R10: 0000000000000001 R11: 0001eb2117e00d55 .... ... NOTE: Currently crash tools doesn't look at ELF notes in the dump on ppc64. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Use #define for max slb entriesAneesh Kumar K.V3-4/+5
Instead of opencoding 64 use MAX_SLB_ENTRIES. We don't update the kernel header here. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Update slb array with correct index values.Aneesh Kumar K.V1-2/+15
Without this, a value of rb=0 and rs=0 results in replacing the 0th index. This can be observed when using gdb remote debugging support. (gdb) x/10i do_fork 0xc000000000085330 <do_fork>: Cannot access memory at address 0xc000000000085330 (gdb) This is because when we do the slb sync via kvm_cpu_synchronize_state, we overwrite the slb entry (0th entry) for 0xc000000000085330 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: Add helper for KVM_PPC_RTAS_DEFINE_TOKENDavid Gibson2-0/+21
Recent PowerKVM allows the kernel to intercept some RTAS calls from the guest directly. This is used to implement the more efficient in-kernel XICS for example. qemu is still responsible for assigning the RTAS token numbers however, and needs to tell the kernel which RTAS function name is assigned to a given token value. This patch adds a convenience wrapper for the KVM_PPC_RTAS_DEFINE_TOKEN ioctl() which is used for this purpose. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25PPC: Fix L2CR write accessesAlexander Graf1-12/+17
Commit 2345f1c01 was supposed to render L2CR writes into noops. Instead, it made them illegal instruction traps which apparently didn't confuse XNU, but can easily confuse other OSs. Fix it up by actually doing nothing when we write to L2CR. Reported-by: Julio Guerra <guerr@julio.in> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Julio Guerra <guerr@julio.in>
2013-10-25target-ppc: Little Endian Correction to Load/Store Vector ElementTom Musta1-0/+2
The Load Vector Element (lve*x) and Store Vector Element (stve*x) instructions not only byte-swap in Little Endian mode, they also invert the element that is accessed. For example, the RTL for lvehx contains this: eb <-- EA[60:63] if Big-Endian byte ordering then VRT[8*eb:8*eb+15] <-- MEM(EA,2) else VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2) This patch adds the element inversion, as described in the last line of the RTL. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-18Merge remote-tracking branch 'bonzini/configure' into stagingAnthony Liguori1-1/+1
# By Peter Maydell (3) and Ákos Kovács (2) # Via Paolo Bonzini * bonzini/configure: ui/Makefile.objs: delete unnecessary cocoa.o dependency default-configs/: CONFIG_GDBSTUB_XML removed Makefile.target: CONFIG_NO_* variables removed rules.mak: New string testing functions rules.mak: New logical functions for handling y/n values
2013-10-16Makefile.target: CONFIG_NO_* variables removedÁkos Kovács1-1/+1
CONFIG_NO_* variables replaced with the lnot logical function Signed-off-by: Ákos Kovács <akoskovacs@gmx.com> [PMM: fixed a few CONFIG_NO_* uses that were missed] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-10-11Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2-9/+5
# By Richard Henderson # Via Richard Henderson * rth/tcg-pull: exec: Add both big- and little-endian memory helpers tcg: Add qemu_ld_st_i32/64 tcg: Add TCGMemOp configure: Remove CONFIG_QEMU_LDST_OPTIMIZATION tcg: Add tcg-be-ldst.h tcg: Add tcg-be-null.h exec: Delete is_tcg_gen_code and GETRA_EXT tcg-aarch64: Update to helper_ret_*_mmu routines tcg: Merge tcg_register_helper into tcg_context_init tcg: Add tcg-runtime.c helpers to all_helpers tcg: Put target helper data into an array. tcg: Remove stray semi-colons from target-*/helper.h tcg: Move helper registration into tcg_context_init target-m68k: Rename helpers.h to helper.h tcg: Use a GHashTable for tcg_find_helper tcg: Delete tcg_helper_get_name declaration tcg-hppa: Remove tcg backend Message-id: 1381440525-6666-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-5/+5
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber1-3/+0
Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-20cpu: Move cpu state syncs up into cpu_dump_state()James Hogan1-2/+0
The x86 and ppc targets call cpu_synchronize_state() from their *_cpu_dump_state() callbacks to ensure that up to date state is dumped when KVM is enabled (for example when a KVM internal error occurs). Move this call up into the generic cpu_dump_state() function so that other KVM targets (namely MIPS) can take advantage of it. This requires kvm_cpu_synchronize_state() and cpu_synchronize_state() to be moved out of the #ifdef NEED_CPU_H in <sysemu/kvm.h> so that they're accessible to qom/cpu.c. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Alexander Graf <agraf@suse.de> Cc: Gleb Natapov <gleb@redhat.com> Cc: qemu-ppc@nongnu.org Cc: kvm@vger.kernel.org Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-1/+1
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand macros. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-03Merge branch 'tcg-next' of git://github.com/rth7680/qemuAurelien Jarno2-1/+3
* 'tcg-next' of git://github.com/rth7680/qemu: (29 commits) tcg-i386: Make use of zero-extended memory helper routines tcg: Introduce zero and sign-extended versions of load helpers exec: Split softmmu_defs.h target: Include softmmu_exec.h where forgotten exec: Rename USUFFIX to LSUFFIX tcg-i386: Don't perform GETPC adjustment in TCG code exec: Reorganize the GETRA/GETPC macros configure: Allow x32 as a host tcg-i386: Adjust tcg_out_tlb_load for x32 tcg-i386: Use intptr_t appropriately tcg: Fix jit debug for x32 tcg: Use appropriate types in tcg_reg_alloc_call tcg: Change tcg_out_ld/st offset to intptr_t tcg: Change tcg_gen_exit_tb argument to uintptr_t tcg: Use uintptr_t in TCGHelperInfo tcg: Change relocation offsets to intptr_t tcg: Change memory offsets to intptr_t tcg: Change frame pointer offsets to intptr_t tcg: Define TCG_ptr properly tcg: Define TCG_TYPE_PTR properly ...
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+2
Several targets forgot to include softmmu_exec.h, which would break them with a header cleanup to follow. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02PPC: KVM: Compile fix for qemu_notify_eventAlexander Graf1-0/+1
The function qemu_notify_event is defined by a header that we don't include in the PPC KVM code. Include it to get the code building again. target-ppc/kvm_ppc.c: In function 'kvmppc_timer_hack': target-ppc/kvm_ppc.c:26:5: error: implicit declaration of function 'qemu_notify_event' [-Werror=implicit-function-declaration] target-ppc/kvm_ppc.c:26:5: error: nested extern declaration of 'qemu_notify_event' [-Werror=nested-externs] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-09-02target-ppc: Use #define instead of opencoding SLB valid bitAneesh Kumar K.V1-1/+1
Use SLB_ESID_V instead of (1 << 27) in the code Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-09-02target-ppc: fix bit extraction for FPBF and FPLAurelien Jarno1-2/+2
Bit extraction for the FP BF and L field of the MTFSFI and MTFSF instructions is wrong and doesn't match the reference manual (which explain the bit number in big endian format). It has been broken in commit 7d08d85645def18eac2a9d672c1868a35e0bcf79. This patch fixes this, which in turn fixes the problem reported by Khem Raj about the floor() function of libm. Reported-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> CC: qemu-stable@nongnu.org (1.6) Signed-off-by: Alexander Graf <agraf@suse.de>
2013-09-02target-ppc: POWER7 supports the MSR_LE bitAnton Blanchard1-1/+1
Add MSR_LE to the msr_mask for POWER7. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-09-02target-ppc: USE LPCR_ILE to control exception endian on POWER7Anton Blanchard2-0/+12
On POWER7, LPCR_ILE is used to control what endian guests take their exceptions in so use it instead of MSR_ILE. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-08-26Merge remote-tracking branch 'stefanha/block' into stagingAnthony Liguori2-7/+7
# By Alex Bligh (32) and others # Via Stefan Hajnoczi * stefanha/block: (42 commits) win32-aio: drop win32_aio_flush_cb() aio-win32: replace incorrect AioHandler->opaque usage with ->e aio / timers: remove dummy_io_handler_flush from tests/test-aio.c aio / timers: Remove legacy interface aio / timers: Switch entire codebase to the new timer API aio / timers: Add scripts/switch-timer-api aio / timers: Add test harness for AioContext timers aio / timers: convert block_job_sleep_ns and co_sleep_ns to new API aio / timers: Convert rtc_clock to be a QEMUClockType aio / timers: Remove main_loop_timerlist aio / timers: Rearrange timer.h & make legacy functions call non-legacy aio / timers: Add qemu_clock_get_ms and qemu_clock_get_ms aio / timers: Remove legacy qemu_clock_deadline & qemu_timerlist_deadline aio / timers: Remove alarm timers aio / timers: Add documentation and new format calls aio / timers: Use all timerlists in icount warp calculations aio / timers: Introduce new API timer_new and friends aio / timers: On timer modification, qemu_notify or aio_notify aio / timers: Convert mainloop to use timeout aio / timers: Convert aio_poll to use AioContext timers' deadline ... Message-id: 1377202298-22896-1-git-send-email-stefanha@redhat.com Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh2-7/+7
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-20Convert stderr message calling error_get_pretty() to error_report()Seiji Aguchi1-1/+2
Convert stderr messages calling error_get_pretty() to error_report(). Timestamp is prepended by -msg timstamp option with it. Per Markus's comment below, A conversion from fprintf() to error_report() is always an improvement, regardless of error_get_pretty(). http://marc.info/?l=qemu-devel&m=137513283408601&w=2 But, it is not reasonable to convert them at one time because fprintf() is used everwhere in qemu. So, it should be done step by step with avoiding regression. Signed-off-by: Seiji Aguchi <seiji.aguchi@hds.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2013-08-07target-ppc: Add POWER5+ v2.1 CPU modelAndreas Färber2-0/+3
Let's avoid -cpu host barfing at this PVR. Linux recognizes it as "POWER5+ (gs) v2.1". Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-5-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Prepare POWER5P CPU familyAndreas Färber2-2/+104
It is ISA 2.03. Modelled as 970FX minus AltiVec flag. Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-4-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Turn POWER5gr CPU into alias for POWER5Andreas Färber2-3/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-3-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Turn POWER5gs CPU into alias for POWER5+Andreas Färber2-3/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-2-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Fix POWER7+ modelAndreas Färber2-3/+4
Commit 03a15a5436ed7723f406f15cc3798aa9991e75b5 claimed to add a POWER7+ model but instead added a "POWER7P" model, with an unhelpful "POWER7P" description on top. Fix this to "POWER7+" as we already have "POWER3+", "POWER4+" and "POWER5+" and there being no reason to deviate with the user-visible command line -cpu POWER7P from the marketing name POWER7+. Further, don't needlessly deviate from the scheme of naming PVR constant, QOM type and device description after the exact revision that is in fact encoded in the PVR used. That way, we can change the user-friendly alias -cpu POWER7+ to point to a different revision if we so desire, while not polluting the type namespace. This naming scheme is sensible and completely orthogonal to how PVRs may or may not get matched to CPU types. Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375736387-8429-1-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-05target-ppc: Add POWER7+ CPU modelAlexey Kardashevskiy2-0/+3
This patch adds CPU PVR definition for POWER7+. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1375412374-24701-1-git-send-email-aik@ozlabs.ru Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-30target-ppc: Suppress TCG instruction emulation warnings for qtestAndreas Färber1-1/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375106733-832-2-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29target-ppc/kvm.c: Rename 'dprintf' to 'DPRINTF'Peter Maydell1-26/+26
'dprintf' is the name of a POSIX standard function so we should not be stealing it for our debug macro. Rename to 'DPRINTF' (in line with a number of other source files.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: MORITA Kazutaka <morita.kazutaka@lab.ntt.co.jp> Acked-by: Richard Henderson <rth@twiddle.net> Acked-by: Kevin Wolf <kwolf@redhat.com> Message-id: 1375100199-13934-4-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori1-0/+2
QOM CPUState refactorings * Fix x86 cpu-add * Change KVM PMU behavior for 1.6 # gpg: Signature made Mon 29 Jul 2013 10:28:18 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Eduardo Habkost (2) and Andreas Färber (1) # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: target-i386: Disable PMU CPUID leaf by default target-i386: Pass X86CPU object to cpu_x86_find_by_name() cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
2013-07-29pseries: savevm support with KVMAlexey Kardashevskiy2-0/+91
At present, the savevm / migration support for the pseries machine will not work when KVM is enabled. That's because KVM manages the guest's hash page table in the host kernel, so qemu has no visibility of it. This patch fixes this by using new kernel interfaces to extract and reinsert the guest's hash table during the migration process. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1374175984-8930-11-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29spapr-tce: make sPAPRTCETable a proper deviceAnthony Liguori1-2/+2
Model TCE tables as a device that's hooked up as a child object to the owner. Besides the code cleanup, we get a few nice benefits: 1) free actually works now (it was dead code before) 2) the TCE information is visible in the device tree 3) we can expose table information as properties such that if we change the window_size, we can use globals to keep migration working. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-6-git-send-email-aliguori@us.ibm.com [dwg: pseries: savevm support for PAPR TCE tables] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [alexey: ppc kvm: fix to compile] Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29target-ppc: Convert ppc cpu savevm to VMStateDescriptionAlexey Kardashevskiy4-93/+451
The savevm code for the powerpc cpu emulation is currently based around the old register_savevm() rather than register_vmstate() method. It's also rather broken, missing some important state on some CPU models. This patch completely rewrites the savevm for target-ppc, using the new VMStateDescription approach. Exactly what needs to be saved in what configurations has been more carefully examined, too. This introduces a new version (5) of the cpu save format. The old load function is retained to support version 4 images. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-2-git-send-email-aliguori@us.ibm.com [aik: ppc cpu savevm convertion fixed to use PowerPCCPU instead of CPUPPCState] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-0/+2
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code. This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed". The reason for the failure is that CPUClass::kvm_fd is not yet initialized in the following call graph: ->x86_cpu_realizefn ->x86_cpu_apic_realize ->qdev_init ->device_set_realized ->device_reset (hotplugged == 1) ->apic_reset_common ->vapic_base_update ->kvm_apic_vapic_base_update This causes attempted KVM vCPU ioctls to fail. By contrast, in the non-hotplug case the APIC is reset much later, when the vCPU is already initialized. As a quick and safe solution, move the qemu_init_vcpu() call back into the targets' realize functions. Reported-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Acked-by: Igor Mammedov <imammedo@redhat.com> (for i386) Tested-by: Jia Liu <proljc@gmail.com> (for openrisc) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XMLAndreas Färber1-0/+5
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field. Use first_cpu for qSupported and qXfer:features:read: for now. Add a stub for xml_builtin. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-2/+16
Completes migration of target-specific code to new target-*/gdbstub.c. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-8/+8
This avoids polluting the global namespace with a non-prefixed macro and makes it obvious in the call sites that we return. Semi-automatic conversion using, e.g., sed -i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target-*/gdbstub.c followed by manual tweaking for sparc's GET_REGA() and Coding Style. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26target-ppc: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+122
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+2
CPUState::gdb_num_regs replaces num_g_regs. CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS. Allows building gdb_register_coprocessor() for xtensa, too. As a side effect this should fix coprocessor register numbering for SMP. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23gdbstub: Change gdb_register_coprocessor() argument to CPUStateAndreas Färber1-7/+8
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber3-1/+7
Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+5
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+8
This moves setting the Program Counter from gdbstub into target code. Use vaddr type as upper-bound replacement for target_ulong. Signed-off-by: Andreas Färber <afaerber@suse.de>
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-30 15:34:19 +0000