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2016-09-15Remove unused function declarationsLadi Prosek2-3/+0
Unused function declarations were found using a simple gcc plugin and manually verified by grepping the sources. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-09-07ppc: Improve a few more helper flagsBenjamin Herrenschmidt1-7/+7
Mostly turn "store" type of helpers into TCG_CALL_NO_WG because they can take exceptions. Also fixup_thrm doesn't read nor write the tracked environment. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Improve the exception helpers flagsBenjamin Herrenschmidt1-2/+2
They generate exceptions, but they don't update the environment Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Improve flags for helpers loading/writing the time facilitiesBenjamin Herrenschmidt1-21/+21
Those helpers never load from or store to the TCG tracked environment, not do they generate synchronous exceptions (they might generate an asynchronous interrupt but that's not an issue here). So we can make them all use TCG_CALL_NO_RWG Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't generate dead code on unconditional branchesBenjamin Herrenschmidt1-5/+9
We are always generating the "else" case of the condition even when generating an unconditional branch that will never hit it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt11-20/+20
Also while at it, group the #include statements in translate.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add extswsli[.] instructionNikunj A Dadhania1-0/+28
extswsli : Extend Sign Word & Shift Left Immediate Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vsrv instructionVivek Andrew Sha4-0/+20
Adds Vector Shift Right Variable instruction. Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reverse the order of computation to avoid temporary array ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vslv instructionVivek Andrew Sha4-0/+20
vslv: Vector Shift Left Variable Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vcmpnez[b,h,w][.] instructionsSwapnil Bokade4-0/+54
Adds following instructions: vcmpnezb[.]: Vector Compare Not Equal or Zero Byte vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword vcmpnezw[.]: Vector Compare Not Equal or Zero Word Signed-off-by: Swapnil Bokade <bokadeswapnil@gmail.com> [ collapse switch case ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vabsdu[b,h,w] instructionsSandipan Das4-3/+39
Adds following instructions: vabsdub: Vector Absolute Difference Unsigned Byte vabsduh: Vector Absolute Difference Unsigned Halfword vabsduw: Vector Absolute Difference Unsigned Word Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> [ use ISA300 define. Drop etype ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add dtstsfi[q] instructionsSandipan Das4-0/+71
DFP Test Significance Immediate [Quad] Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: implement branch-less divd[o][.]Nikunj A Dadhania1-22/+26
Similar to divw, implement branch-less divd. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: implement branch-less divw[o][.]Nikunj A Dadhania1-25/+23
While implementing modulo instructions figured out that the implementation uses many branches. Change the logic to achieve the branch-less code. Undefined value is set to dividend in case of invalid input. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: load/store multiple and string insns don't do LEBenjamin Herrenschmidt1-0/+29
Just generate an alignment interrupt Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Use a helper to generate "LE unsupported" alignment interruptsBenjamin Herrenschmidt1-3/+8
Some operations aren't allowed in LE mode, use a helper rather than open coding the exception generation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't set access_type on all load/stores on hash64Benjamin Herrenschmidt1-1/+3
We don't use it so let's not generate the updates. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Fix CFAR updatesBenjamin Herrenschmidt1-4/+4
We were one instruction off Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Speed up dcbzBenjamin Herrenschmidt2-28/+29
Use tlb_vaddr_to_host to do a fast path single translate for the whole cache line. Also make the reservation check match the entire range. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Handle unconditional (always/never) traps at translation timeBenjamin Herrenschmidt1-6/+43
We don't need to call a helper for trap always and trap never which are used by Linux under some circumstances. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Don't generate the helper call when trapping always Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make alignment exceptions suck lessBenjamin Herrenschmidt2-5/+6
The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in dcbz and lscbxBenjamin Herrenschmidt2-8/+5
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP if not taking alignment exceptionsBenjamin Herrenschmidt1-2/+1
Move the NIP update to after the conditional branch so that we don't do it if we aren't going to take the alignment exception Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt2-10/+4
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP BookE 2.06 tlbweBenjamin Herrenschmidt2-7/+6
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt4-14/+5
This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt2-22/+13
This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Fix source NIP on SLB related interruptsBenjamin Herrenschmidt1-8/+8
We need to pass it to the raise helper since we don't update it before the calls. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt3-122/+91
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt2-11/+6
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt3-20/+32
Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean this all up by always having the nip already set to the right instruction when taking the fault. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fix trivial checkpatch warning] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: FP exceptions are always preciseBenjamin Herrenschmidt1-5/+6
We don't implement imprecise FP exceptions and using store_current which sets SRR1 to the *previous* instruction never makes sense for these. So let's be truthful and make them precise, which is allowed by the architecture. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update the NIP in floating point generated codeBenjamin Herrenschmidt2-34/+0
This is no longer necessary as the helpers will properly retrieve the return address. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make float_check_status() pass the return addressBenjamin Herrenschmidt1-27/+40
Instead of relying on NIP having been updated already. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fold in fix to mark function always_inline] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make float_invalid_op_excp() pass the return addressBenjamin Herrenschmidt1-2/+4
Instead of relying on NIP having been updated already Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename fload_invalid_op_excp to float_invalid_op_excpBenjamin Herrenschmidt1-61/+61
No other change Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt3-991/+994
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt3-1065/+1077
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt3-363/+365
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt3-1326/+1336
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt3-1201/+1213
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Provide basic raise_exception_* functionsBenjamin Herrenschmidt2-17/+42
Instead of using the same helpers called from translate.c, let's have a bunch of functions that take the various argument combinations, especially the retaddr which will be needed in subsequent patches, and leave the helpers to be just that, helpers for translate.c We don't yet convert all users, we'll go through them in subsequent patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Fix raise_exception_ra() to properly pass raddr Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania2-54/+155
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Trivial checkpatch fixup] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania1-0/+25
maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the higher dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania1-0/+14
maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add setb instructionVivek Andrew Sha1-0/+22
The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania3-0/+35
Search a byte in the stream of 8bytes provided in the register Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania3-0/+17
Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das3-0/+16
Add ISA3.0 Count trailing zeros double word Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> [ added ISA300 flag ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo dword operationsNikunj A Dadhania1-0/+48
Adding following instructions for ISA3.0 support modud: Modulo Unsigned Dword modsd: Modulo Signed Dword Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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