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path: root/target-sparc/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2008-10-06Show size for unassigned accesses (Robert Reif)blueswir11-1/+1
2008-10-03Rearrange tick functionsblueswir11-0/+7
2008-10-03Fix missing prototype warnings by moving declarationsblueswir11-0/+9
2008-09-22Add software and timer interrupt supportblueswir11-0/+2
2008-09-20Move signal handler prototype back to cpu.hblueswir11-0/+1
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir11-1/+0
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir11-16/+5
2008-09-06Silence gcc warning about constant overflowblueswir11-1/+9
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir11-26/+26
2008-08-29Fix Sparc64 boot on i386 host:blueswir11-6/+32
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir11-39/+49
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir11-3/+5
2008-07-24Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir11-1/+1
2008-07-21Use MMU globals for some MMU trapsblueswir11-1/+2
2008-07-20Make UA200x features selectable, add MMU typesblueswir11-0/+10
2008-07-16Fix MMU miss trapsblueswir11-2/+2
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook1-2/+0
2008-06-30Move CPU save/load registration to common code.pbrook1-0/+2
2008-06-29Add instruction counter.pbrook1-0/+5
2008-06-23Fix compiler warning (Jan Kiszka)blueswir11-1/+2
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir11-6/+27
2008-05-30Fix typo.pbrook1-1/+1
2008-05-30Move clone() register setup to target specific code. Handle fork-like clone.pbrook1-0/+12
2008-05-29MicroSparc I didn't have fsmuld opblueswir11-2/+3
2008-05-29Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard1-2/+0
2008-05-28moved halted field to CPU_COMMONbellard1-1/+0
2008-05-12Wrap long linesblueswir11-1/+1
2008-05-10Remove duplicated fieldblueswir11-1/+0
2008-05-10suppressed fixed registersbellard1-2/+5
2008-05-10Fix compiler warningsblueswir11-7/+7
2008-05-09CPU feature selection supportblueswir11-3/+27
2008-05-04Complete the TCG conversionblueswir11-4/+2
2008-04-23Document the shift valuesblueswir11-6/+12
2008-03-29 Move CPU stuff unrelated to translation to helper.cblueswir11-0/+1
2008-03-16 Convert mulscc to TCG, add cc_src2blueswir11-1/+1
2008-03-13 Convert condition code changing versions of add, sub, logic, and div to TCGblueswir11-0/+5
2008-03-06 Convert exception ops to TCGblueswir11-1/+0
2008-03-05 Convert Sparc64 trap state ops to TCGblueswir11-4/+8
2008-03-02 Convert tick operations to TCGblueswir11-3/+0
2008-02-14 Fix remote debugger memory access problems reported by Matthias Steinblueswir11-5/+8
2008-02-11 Sparc32 MMU register fixes (Robert Reif)blueswir11-0/+4
2007-11-28Use slavio base as boot prom address, rearrange sun4m init codeblueswir11-0/+1
2007-11-25 128-bit float support for user modeblueswir11-0/+3
2007-11-25 More MMU registers (Robert Reif)blueswir11-1/+1
2007-11-10added cpu_model parameter to cpu_init()bellard1-6/+2
2007-11-07 CPU specific boot mode (Robert Reif)blueswir11-1/+1
2007-10-14 Sparc64 hypervisor modeblueswir11-4/+35
2007-10-14 SuperSparc MXCC support (Robert Reif)blueswir11-1/+4
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-0/+11
2007-10-12Unify '-cpu ?' option.j_mayer1-0/+1