summaryrefslogtreecommitdiff
path: root/target-sparc/helper.h
AgeCommit message (Collapse)AuthorFilesLines
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-9/+9
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23SPARC LEON power-down support addedRonald Hecht1-0/+1
Signed-off-by: Ronald Hecht <address@hidden> Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-28target-sparc: rename helper flagsAurelien Jarno1-25/+25
Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Acked-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-07target-sparc: Move taddcctv and tsubcctv out of lineRichard Henderson1-0/+2
The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Move sdivx and udivx out of lineRichard Henderson1-0/+4
The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24target-sparc: Add compiler attribute to some functions which don't returnStefan Weil1-1/+1
helper_raise_exception does not return, nor does do_unaligned_access. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18Sparc: avoid AREG0 for memory access helpersBlue Swirl1-10/+10
Make memory access helpers take a parameter for CPUState instead of relying on global env. Introduce wrappers for load and store ops. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-19Improve "ta 0" shutdownFabien Chouteau1-1/+0
This patch replace the previous implementation with this simplified and more complete version (no shutdown when psret == 1). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26target-sparc: Implement FALIGNDATA inline.Richard Henderson1-1/+0
This is a relatively simple sequence of shifts. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement BMASK/BSHUFFLE.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement ALIGNADDR* inline.Richard Henderson1-1/+0
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not implemeneted at all. However, this is a very simple operation so we're better off doing this inline. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement fpack{16,32,fix}.Richard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement PDIST.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Do exceptions management fully inside the helpers.Richard Henderson1-2/+0
This reduces the size of the individual translation blocks, since we only emit a single call for each FOP rather than three. In addition, clear_float_exceptions expands inline to a single byte store. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Make FPU/VIS helpers const when possible.Richard Henderson1-22/+28
This also removes the unused ENV parameter from these helpers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Pass float64 parameters instead of dt0/1 temporaries.Richard Henderson1-48/+47
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26Sparc: avoid AREG0 for division op helpersBlue Swirl1-4/+4
Make [su]div{,cc} helpers take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26Sparc: avoid AREG0 for softint op helpers and Leon cache controlBlue Swirl1-3/+3
Make softint op helpers and Leon cache irq manager take a parameter for CPUState instead of relying on global env. Move the functions to int{32,64}_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26Sparc: avoid AREG0 for CWP and PSTATE helpersBlue Swirl1-16/+16
Make CWP and PSTATE helpers take a parameter for CPUState instead of relying on global env. Remove wrapper functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23Sparc: avoid AREG0 for lazy condition code helpersBlue Swirl1-2/+2
Make lazy condition code helpers take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23Sparc: avoid AREG0 for float and VIS opsBlue Swirl1-86/+86
Make floating point and VIS ops take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23Sparc: avoid AREG0 for raise_exception and helper_debugBlue Swirl1-2/+2
Make raise_exception() and helper_debug() take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20SPARC64: fix VIS1 SIMD signed compare instructionsTsuneo Saito1-2/+2
The destination registers of SIMD signed compare instructions (fcmp*<16|32>) are not FP registers but general purpose r registers. Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-22Delete unused tb_invalidate_page_rangeBlue Swirl1-1/+0
tb_invalidate_page_range() was intended to be used to invalidate an area of a TB which the guest explicitly flushes from i-cache. However, QEMU detects writes to code areas where TBs have been generated, so his has never been useful. Delete the function, adjust callers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24SPARC: Emulation of Leon3Fabien Chouteau1-0/+1
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-28target-sparc: fix udiv(cc) and sdiv(cc)Aurelien Jarno1-0/+2
Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes on a Debian Etch image. The commit itself is fine, but it triggers a bug due to wrong computation of flags for udiv(cc) and sdiv(cc). This patch only compute cc_src2 for the cc version of udiv/sdiv. It also moves the update of cc_dst and cc_op to the helper, as it is faster doing it here when there is already an helper. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-20target-sparc: Inline some generation of carry for ADDX/SUBX.Richard Henderson1-1/+1
Computing carry is trivial for some inputs. By avoiding an external function call, we generate near-optimal code for the common cases of add+addx (double-word arithmetic) and cmp+addx (a setcc pattern). Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-19target-sparc: Fix compilation with --enable-debug.Richard Henderson1-1/+1
Return a target_ulong from compute_C_icc to match the width of the users. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-08sparc64: use helper_wrpil to check pending irq on writeIgor V. Kovalenko1-0/+1
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Use dynamical computation for condition codesBlue Swirl1-0/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2008-11-17TCG variable type checking.pbrook1-109/+101
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-26Implement UA2005 hypervisor trapsblueswir11-2/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22Add software and timer interrupt supportblueswir11-0/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21Use the new concat_i32_i64 op for std and stdablueswir11-1/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir11-11/+8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Partially convert float128 conversion ops to TCGblueswir11-4/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir11-9/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir11-15/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic float32 ops to TCGblueswir11-18/+29
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir11-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29Fix Sparc64 boot on i386 host:blueswir11-9/+0
- move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19Implement nucleus quad lddablueswir11-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-27Move non-op functions from op_helper.c to helper.c and vice versa.blueswir11-0/+1
Rearrange interrupt handling to match other targets. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22Register op helpersblueswir11-93/+96
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4534 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12Move prototype back to avoid a compiler warningblueswir11-1/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4443 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-10Fix compiler warningsblueswir11-0/+9
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09CPU feature selection supportblueswir11-20/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04Complete the TCG conversionblueswir11-0/+7
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4323 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-21 Convert align checks to TCGblueswir11-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4097 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-27 22:53:11 +0000