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path: root/target-sparc/op_helper.c
AgeCommit message (Expand)AuthorFilesLines
2008-07-08Implement some Ultrasparc cache ASIs used by SILOblueswir11-0/+20
2008-06-20Fix boot problem on i386 host introduced in r4690blueswir11-4/+4
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir11-12/+12
2008-05-29Remove unused (for now) reg_REGWPTR (original patch by Glauber Costa)blueswir11-1/+0
2008-05-27Move non-op functions from op_helper.c to helper.c and vice versa.blueswir11-234/+13
2008-05-25Fix off-by-one unwinding error.pbrook1-6/+0
2008-05-20Remove currently unnecessary alignment maskingblueswir11-57/+57
2008-05-12Wrap long linesblueswir11-44/+84
2008-05-11Remove someexplicit alignment checks (initial patch by Fabrice Bellard)blueswir11-54/+80
2008-05-10suppressed fixed registersbellard1-28/+1
2008-05-10Fix compiler warningsblueswir11-3/+3
2008-05-09CPU feature selection supportblueswir11-47/+56
2008-05-09Move #include to speed up compilationblueswir11-0/+3
2008-05-04Complete the TCG conversionblueswir11-0/+103
2008-04-22Revert the previous patchblueswir11-0/+108
2008-04-22Move 128-bit float emulation under linux-userblueswir11-108/+0
2008-03-21 Convert align checks to TCGblueswir11-0/+6
2008-03-21 Convert save, restore, saved, restored, and flushw to TCGblueswir11-0/+92
2008-03-21 Convert other float and VIS ops to TCGblueswir11-34/+614
2008-03-18 Convert udiv and sdiv ops to TCGblueswir11-0/+44
2008-03-18 Convert CCR and CWP ops to TCGblueswir11-0/+21
2008-03-18 Convert array8/16/32 and alignaddr to TCGblueswir11-0/+31
2008-03-15 Convert ldfsr and stfsr to TCGblueswir11-1/+8
2008-03-05 Convert Sparc64 trap state ops to TCGblueswir11-17/+21
2008-03-04 Convert float helpers to TCG, fix fabsq in the processblueswir11-22/+13
2008-02-24 Modify Sparc32/64 to use TCGblueswir11-280/+318
2008-02-11 Sparc32 MMU register fixes (Robert Reif)blueswir11-8/+14
2008-01-01 More ASIsblueswir11-6/+18
2007-12-30 Nicer debug output for exceptionsblueswir11-4/+104
2007-12-28 Initial support for Sun4d machines (SS-1000, SS-2000)blueswir11-3/+1
2007-12-28 Improved ASI debugging (Robert Reif)blueswir11-14/+58
2007-12-10 Add ASIs (Robert Reif)blueswir11-1/+8
2007-11-28 Fix compilation and warnings on PPC hostblueswir11-0/+17
2007-11-25 128-bit float support for user modeblueswir11-0/+39
2007-11-25 More MMU registers (Robert Reif)blueswir11-6/+17
2007-11-19 Fix MXCC register 64 bit read word order (Robert Reif)blueswir11-4/+4
2007-11-17Break up vl.h.pbrook1-24/+0
2007-11-17 Remove unnecessary register masking (Robert Reif)blueswir11-5/+5
2007-11-17 Fix MXCC error register (Robert Reif)blueswir11-4/+2
2007-11-17 Add MXCC module reset register (Robert Reif)blueswir11-0/+8
2007-11-11removed warningbellard1-1/+1
2007-11-07 CPU specific boot mode (Robert Reif)blueswir11-2/+2
2007-10-29Adjust s390 addresses (the MSB is defined as "to be ignored").ths1-1/+5
2007-10-28 Use shared ctpop64 helperblueswir11-6/+2
2007-10-20 Avoid gcc warningsblueswir11-2/+2
2007-10-20 Fix compiling Sparc64 on PPC hostblueswir11-0/+15
2007-10-17 Use ldq and stq for 8 byte accesses (original patch by Robert Reif)blueswir11-21/+22
2007-10-14 Fix bug in Sparc32 sta op (Robert Reif)blueswir11-1/+1
2007-10-14 Sparc64 hypervisor modeblueswir11-30/+68
2007-10-14 SuperSparc MXCC support (Robert Reif)blueswir11-16/+151
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